FinFET Antifuse Memory Well Structure for High-Voltage Programming
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Solution Overview
Problem
Existing antifuse-type memories with FinFET transistors face challenges in operating at high voltages due to limitations in the design of the well structure and the semiconductor substrate biasing, which affects the reliability and efficiency of programming and reading operations.
Innovation Solution
The proposed antifuse-type memory incorporates a specially designed well structure within a semiconductor substrate, where the P-well region is surrounded by a pickup N-well region and a deep N-well region, allowing the antifuse transistor to receive a higher program voltage and operate effectively. This design includes FinFET transistors as both select and antifuse transistors, with specific biasing voltages applied to the substrate and well regions to support high-voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional well structure and substrate biasing are used in FinFET-based antifuse memory, then the device can be manufactured with standard processes, but the memory cannot operate reliably at high voltages required for programming
Solution Approach 1:
The well structure is segmented into multiple distinct regions: a P-well region containing the antifuse transistor, surrounded by a first N-well region, which is in turn surrounded by a second N-well region. This segmentation allows each region to be independently biased at different voltages, enabling the antifuse transistor to operate at high programming voltages while maintaining device integrity and reliability.
2Productivity
If higher program voltage is applied to rupture the gate dielectric layer, then programming efficiency is improved, but the risk of damaging other components increases
Solution Approach 1:
Different regions of the device are assigned different voltage levels and electrical characteristics tailored to their specific functions. The P-well region where the antifuse transistor operates is locally optimized to withstand high programming voltages, while other regions are maintained at lower voltages appropriate for normal operation, thus achieving high programming efficiency without causing widespread damage.
Solution Approach 2:
The multi-region well structure is designed in advance to provide voltage isolation and protection. The N-well regions act as protective buffers that isolate the high-voltage programming operation from other sensitive components, cushioning against potential voltage-induced damage before it can propagate through the device.
3Use of energy by moving object
If the gate dielectric layer is made thinner to enable lower voltage operation, then power consumption is reduced, but the programming voltage requirement increases
Solution Approach 1:
The gate dielectric layer thickness is optimized for low-power operation, while the segmented well structure provides the necessary high-voltage tolerance through its multi-region design. The P-well and N-well regions create voltage isolation that protects the thin gate dielectric during high-voltage programming operations, allowing the device to benefit from both thin-dielectric low-power operation and high-voltage programming capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the antifuse-type memory to operate reliably at high voltages, ensuring effective programming and reading operations by rupturing the gate dielectric layer of the antifuse transistor under high voltage stress, thus achieving a low-resistance storage state.
Implementation Method 1
If the first bit line receives a ground voltage, the first word line receives an on voltage, the first following control line receives a conducting voltage and the first antifuse control line receives a program voltage when a program action is performed, the first gate dielectric layer of the first antifuse transistor is ruptured
Data Source
AI summary
An antifuse-type memory includes a first memory cell. The first memory cell includes a first select transistor, a first following transistor and a first antifuse transistor. A first drain/source terminal of the first select transistor is connected with a first bit line. A gate terminal of the first select transistor is connected with a first word line. A first drain/source terminal of the first following transistor is connected with a second drain/source terminal of the first select transistor. A gate terminal of the first following transistor is connected with a first following control line. The first antifuse transistor includes a first fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. The first gate structure includes a first gate dielectric layer and a first gate layer. The first gate layer is connected with a first antifuse control line.