Memory Bit-Line Layout With Local Interconnects for Lower Resistance
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Solution Overview
Problem
Increasing the length and decreasing the size of word-lines and bit-lines in memory arrays leads to increased resistance, causing variations in read signals and reduced memory window, resulting in errors in data reading and writing.
Innovation Solution
Incorporating a local interconnect that extends in parallel to the bit-line, providing an alternative path for signals and reducing the resistance by increasing the cumulative cross-sectional area for signal travel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the length of bit-lines is increased to accommodate larger memory arrays, then the memory capacity is improved, but the resistance of bit-lines increases causing signal degradation
Solution Approach 1:
The patent divides the bit-line into multiple segments by introducing local interconnects at intermediate points. Each segment between adjacent interconnects is shorter, reducing the resistance accumulation along the bit-line. This segmentation allows the memory array to be scaled while maintaining signal integrity through multiple low-resistance paths.
Solution Approach 2:
The patent introduces local interconnects as intermediary structures between the bit-line and memory devices. These interconnects act as mediators that provide alternative current paths, reducing the overall resistance of the bit-line and mitigating signal degradation in large memory arrays.
2Quantity of substance
If the size of bit-lines is decreased to increase memory density, then the memory capacity is improved, but the resistance increases causing variations in read signals
Solution Approach 1:
By segmenting the bit-line with local interconnects, the patent reduces the effective length of each bit-line segment. This allows for narrower wire widths while maintaining acceptable resistance levels, thereby increasing memory density without sacrificing read signal consistency.
Solution Approach 2:
The patent adds a vertical dimension to the interconnect structure by stacking multiple interconnect layers. This dimensional change provides additional parallel paths for current flow, reducing resistance without increasing the planar footprint, thus enabling higher density with improved signal consistency.
3Length of stationary object
If the length of word-lines and bit-lines is increased, then the memory array size is improved, but the resistance increases causing reduced memory window
Solution Approach 1:
The patent applies segmentation to both word-lines and bit-lines by introducing local interconnects that divide these conductors into shorter segments. This reduces the cumulative resistance in large memory arrays, preserving the memory window and enabling reliable operation of scaled-up memory structures.
Data Source
AI summary
The present disclosure relates integrated chip structure. The integrated chip structure includes a memory array having a plurality of memory devices arranged in a plurality of rows and a plurality of columns. A word-line is coupled to a first set of the plurality of memory devices disposed within a first row of the plurality of rows. A bit-line is coupled to a second set of the plurality of memory devices disposed within a first column of the plurality of columns. A local interconnect extends in parallel to the bit-line and is coupled to the bit-line and two or more of the second set of the plurality of memory devices. The local interconnect is coupled to the bit-line by a plurality of interconnect vias that are between the local interconnect and the bit-line.