3D Stacked Memory Layer Structure for Higher DRAM Density
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Solution Overview
Problem
The traditional 1T0C type DRAM faces challenges in increasing memory density due to the difficulty and cost associated with shrinking transistor sizes, as well as the limitations of using a substrate as the active layer in a planar configuration.
Innovation Solution
A semiconductor structure is proposed where the active layer of the transistor is extended vertically and independently provided relative to the substrate, allowing for a three-dimensional configuration of the memory layer with multiple transistors stacked in a vertical direction, thereby increasing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the substrate is used as the active layer in a planar configuration, then the manufacturing process is simpler, but the memory density is limited
Solution Approach 1:
The patent transitions from a planar (2D) configuration where the substrate serves as the active layer to a three-dimensional (3D) structure where the active layer is extended vertically. This dimensional change allows memory cells to be stacked in the vertical direction, significantly increasing the number of transistors per unit area and thereby improving memory density without complicating the fundamental manufacturing process
2Quantity of substance
If the transistor size is shrunk to increase memory density, then the memory density increases, but the process difficulty and technical cost increase
Solution Approach 1:
Instead of shrinking transistor dimensions in the planar direction, the patent extends the active layer vertically to create a 3D structure. This approach increases memory density by stacking transistors in the vertical direction while maintaining larger, easier-to-manufacture transistor footprints, thereby avoiding the process difficulty and cost associated with extreme miniaturization
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure by extending the active layer in the vertical direction rather than reducing horizontal dimensions. This parameter change allows for increased memory density through vertical stacking while maintaining manufacturing feasibility by avoiding excessive shrinkage of critical transistor dimensions
Data Source
AI summary
A semiconductor structure includes a substrate and at least one memory layer stacked on a same side of the substrate in a vertical direction. The memory layer includes a first signal line layer, at least one transistor layer, a second signal line layer and at least one gating line layer. The first signal line layer includes a plurality of first signal lines spaced apart, each transistor layer includes a plurality of transistors spaced apart, the second signal line layer includes a plurality of second signal lines spaced apart, and each gating line layer includes a plurality of gating lines spaced apart. One of the first signal line and the second signal line is a reference voltage line and another one of the first signal line and the second signal line is a read-write line. A gate layer of the transistor is connected to the gating line.