3D Memory Word Line Patterning for Aspect Ratio Stability
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving optimal aspect ratios during the formation of memory arrays, which can lead to defects and structural instability, affecting memory cell density and reliability.
Innovation Solution
A multiple-patterning process is employed to form word lines and transistors in a semiconductor memory array, allowing for low pattern density and reducing the aspect ratio of the multilayer stack, thereby avoiding twisting or collapsing during formation and improving structural stability and memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single patterning process is used to form word lines and transistors, then the manufacturing process is simpler, but the aspect ratio becomes too high causing twisting or collapsing and reducing structural stability
Solution Approach 1:
The single patterning process is divided into multiple sequential patterning steps. First, a preliminary pattern is formed with relaxed aspect ratio requirements, then additional patterning steps complete the final word line and transistor patterns. This segmentation allows each step to operate at optimal pattern density, preventing the multilayer stack from twisting or collapsing during formation.
2Quantity of substance
If high pattern density is used in patterning, then memory cell density can be increased, but the multilayer stack becomes unstable and twists or collapses
Solution Approach 1:
A preliminary patterning step is performed first to establish initial patterns with low pattern density. This preliminary action creates a stable foundation that prevents the multilayer stack from twisting or collapsing. Subsequent patterning steps then add additional features to achieve the desired memory cell density without compromising structural integrity.
Data Source
AI summary
In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.