Memory Bank Transfer Bus for Direct Low-Power Data Routing

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Solution Overview

Problem

Current memory systems face inefficiencies in data transfer between memory banks, particularly due to the reliance on external buses and the need for separate internal and external data buses, which increases power consumption and processing time.

Innovation Solution

The implementation of a bank-to-bank transfer (BBT) bus that allows for direct data transfer between memory banks without using external buses, optimizing the path for minimal power consumption and time by determining the shortest path for data transfer, enabling parallel and bi-directional transfers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If data is transferred between memory banks using external buses, then data transfer can be performed, but power consumption increases and processing time is extended

Engineering Contradiction:
Improvepower consumptionVSAvoidbus structure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent extracts the data transfer function from the external bus system and implements a dedicated internal bank-to-bank transfer bus. This separates the internal data transfer path from external communication paths, allowing internal transfers to occur without involving external buses, thereby reducing power consumption while maintaining transfer capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the data transfer system into multiple independent bus paths: external buses for external communication and an internal bank-to-bank transfer bus for internal data movement. This segmentation allows selective use of appropriate transfer paths based on whether data needs to leave the memory device, reducing unnecessary power consumption from external bus operations

Inventive Principle:
Principle #1Segmentation

2Productivity

If separate internal and external data buses are used, then data transfer functionality is provided, but processing time increases

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidprocessing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent prepares the internal bank-to-bank transfer bus in advance as a dedicated pathway for internal data movement. By having this transfer path pre-established and independent from external bus operations, the system can immediately initiate internal transfers without waiting for external bus availability, reducing processing time

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The internal bank-to-bank transfer bus acts as an intermediary that facilitates direct data movement between memory banks without requiring external bus involvement. This intermediary pathway eliminates the time-consuming steps of routing data through external buses and back, significantly reducing processing time for internal transfers

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If external buses are used for bank-to-bank transfer, then data can be moved between banks, but power consumption increases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements a localized internal transfer bus specifically for bank-to-bank data movement within the memory device. This local transfer path eliminates the need for data to traverse the entire external bus interface, reducing energy consumption by limiting the transfer to only the necessary local pathway within the memory chip

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3625801B1Bank to bank data transfer
Publication Date: 2022.10.05 MICRON TECHNOLOGY INC
  • EP3625801B1 patent drawingFigure 1A
  • EP3625801B1 patent drawingFigure 1B
  • EP3625801B1 patent drawingFigure 2

AI summary

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.