Variable-Resistor Memory Cells With Backside Source Lines for Read Margin
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Solution Overview
Problem
The increasing miniaturization of semiconductor memory devices leads to increased resistance in metal lines, which reduces the read margin and causes mismatch errors between memory cells close to and distant from the sense amplifier, affecting normal read operations.
Innovation Solution
The semiconductor memory device design includes a first memory cell with a variable resistor element and a cell transistor connected through a source-drain electrode, where the substrate has a first surface connected to the second source-drain electrode and a second surface opposing the first, with a bitline connected through the variable resistor element and a source line disposed on the second surface, reducing the resistance of metal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of metal lines is decreased to achieve miniaturization, then the integration density is improved, but the resistance of metal lines is increased
Solution Approach 1:
The source line is moved from the first surface of the substrate to the second surface of the substrate, utilizing the third dimension (vertical stacking) to separate the source line from the bitline and memory cells. This dimensional change allows the source line to have a larger cross-sectional area and shorter path length, reducing its resistance without increasing the planar footprint of the memory cell, thus resolving the contradiction between miniaturization and read margin.
2Device complexity
If the size of metal lines is decreased for high integration, then the device complexity is reduced, but the read margin mismatch between memory cells occurs
Solution Approach 1:
By relocating the source line to the second surface of the substrate and establishing vertical connections through the substrate thickness, the invention creates more uniform current paths for all memory cells in the array. This dimensional reconfiguration ensures that memory cells at different locations (close to or distant from sense amplifiers) experience similar resistance characteristics, eliminating read margin mismatch while maintaining simple planar cell structures.
3Manufacturing precision
If the resistance of metal lines is increased due to miniaturization, then the manufacturing precision is improved, but the power efficiency is reduced
Solution Approach 1:
The invention utilizes vertical stacking and substrate thickness to create low-resistance current paths for the source line, which carries the read current through the memory array. By moving the source line to the second surface and using through-substrate connections, the current path length and resistance are reduced, allowing fine-pitched bitlines and source lines to be manufactured with high precision while maintaining low power consumption through the reduced resistive losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces the resistance of metal lines, enhances power efficiency, and increases the read margin, thereby improving the accuracy and reducing the size of memory cells.
Implementation Method 1
The MRAM stores data in a memory cell using a change in resistance of a magnetic tunnel junction (MTJ) element. The resistance of the MTJ element varies depending on whether a magnetization direction of a free layer is the same as that of a pinned layer.
Implementation Method 2
An RRAM may have different resistances depending on the characteristics of a resistance change caused by a change of a magnetic field formed in an insulating layer disposed between two metal layers.
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A semiconductor memory device includes a first memory cell (MC1) including a first variable resistor element (VR1) and a first cell transistor (CT1) connected to the first variable resistor element (VR1) through a first source-drain electrode (SD1), a substrate (200) having a first surface (201) connected to the second source-drain electrode (SD2) of the first cell transistor (CT1) and a second surface (202) opposing the first surface (201), a first bitline (BL1) connected to the first source-drain electrode (SD1) of the first cell transistor (CT1) through the first variable resistor element (VR1), and a first source line (SL1) disposed on the second surface (202) of the substrate (200) and connected to the second source-drain electrode (SD2).