Local Bit-Select Circuit for Fast Read-Before-Write Suppression
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Solution Overview
Problem
In static random-access memory (SRAM) designs, the 'Fast Read before Write' issue occurs when cells are slow to write but fast to read, causing local bit lines to be pulled down to ground, making them un-writable due to manufacturing process variations and timing mismatches, leading to performance slowdowns and un-writeable states.
Innovation Solution
A local bit-select circuit with gated cross-coupled PFETs is implemented, which includes pull-up and pull-down devices connected to read and write global bitlines, preventing the local bit lines from being pulled down by the write transistor during a read operation, ensuring the cell remains writable by blocking conduction paths and maintaining the state dictated by write signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cells are designed for fast read access, then read speed is improved, but write capability deteriorates due to local bit lines being pulled down to ground
Solution Approach 1:
The patent applies preliminary anti-action by implementing pull-up devices that preemptively counteract the harmful pull-down effect on local bit lines before it can prevent write operations. The pull-up devices are activated in response to detect write operations to maintain bit line voltage levels and prevent the bit lines from being pulled down to ground, thus preserving write capability while allowing fast read access.
Solution Approach 2:
The patent uses pull-up devices as intermediary elements between the write transistor and the local bit lines. These intermediary devices mediate the interaction by providing an opposing pull-up force that balances the pull-down effect, allowing the write operation to proceed without completely pulling the bit lines down to ground level.
2Adaptability or versatility
If manufacturing process variations are present, then device performance varies, but Fast Read before Write errors increase
Solution Approach 1:
The patent applies beforehand cushioning by providing pull-up devices that are prepared and positioned to counteract potential harmful effects before they occur. These devices act as a cushion or buffer that prevents write operations from failing due to process variations, ensuring that even when manufacturing variations cause unexpected behavior, the write operation can still complete successfully.
3Ease of operation
If timing mismatches occur between read and write operations, then operational flexibility is maintained, but write failures increase
Solution Approach 1:
The patent implements feedback mechanisms where the state of local bit lines is continuously monitored during operations. When a write operation is detected or when bit line voltage drops below a threshold, the pull-up devices are activated to correct the voltage level, providing real-time feedback control that ensures write operations succeed regardless of timing mismatches between read and write operations.
Data Source
AI summary
Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.