Dynamic Decode Circuit With Delayed Precharge for Glitch Control
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Solution Overview
Problem
Dynamic decode circuits in dynamic logic face performance issues due to premature discharging of gates, leading to glitches and reduced efficiency, especially when cascading gates, as they rely on precharge states that cannot be restored until the next clock cycle.
Innovation Solution
The dynamic decode circuit is designed with a delayed precharge function that begins precharge a predetermined time after the evaluate period ends, and includes a special precharge circuit with a delayed evaluation clock signal to reduce the likelihood of unwanted glitches, allowing the output to remain active longer and improving performance by reducing transistor size and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dynamic decode circuits use precharge states during clock cycles, then the circuits can operate in dynamic logic mode with faster switching, but premature discharging of gates occurs leading to glitches and reduced reliability
Solution Approach 1:
The patent applies preliminary action by precharging the decode circuit gates before the evaluate phase begins. The precharge transistor activates early in the clock cycle to charge all decode gates to a known state, ensuring they are ready for evaluation without experiencing premature discharging glitches during the active evaluation phase.
2Productivity
If the precharge phase starts immediately after evaluate phase, then the circuit resets quickly for the next cycle, but the output signal duration is reduced and performance is limited
Solution Approach 1:
The patent implements periodic action by structuring the clock signal with distinct precharge and evaluate phases. The precharge phase is timed to occur during the low period of the clock signal, while evaluation occurs during the high period, creating a rhythmic periodic operation that optimizes both output duration and reset speed for sustained high-performance operation.
3Area of stationary object
If transistor size is reduced to improve density, then more circuits can be integrated, but the circuits become more susceptible to glitches and noise
Solution Approach 1:
The patent applies preliminary anti-action by using the precharge transistor to proactively counteract potential glitch effects before they can propagate. By charging all decode gates to a known high state at the beginning of each cycle, the circuit preemptively prevents unwanted discharge glitches from smaller transistors, allowing reduced transistor sizes without sacrificing noise immunity.
Data Source
AI summary
A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.