Buffer Circuit Switching for Faster Output Fall Time
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Solution Overview
Problem
Buffer circuits in active-matrix display devices face challenges in shortening output signal fall time while reducing circuit area and power consumption, as increasing transistor driving performance for faster fall times leads to increased leak current and higher power consumption.
Innovation Solution
A buffer circuit driving method that utilizes two transistors connected in series, where both transistors switch to conducting states during specific periods of the clock signal, allowing the output signal to drop more rapidly without increasing circuit area or power consumption, with the second transistor's voltage set lower than the first to enhance fall time reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor driving performance is increased to shorten output signal fall time, then fall time is reduced, but leak current increases and power consumption increases
Solution Approach 1:
The buffer circuit is divided into two separate transistors (first transistor and second transistor) that operate at different voltage levels. The first transistor handles the high-voltage-to-low-voltage transition while the second transistor handles the low-voltage discharge path, segmenting the current path to reduce overall leak current while maintaining fast fall time performance
Solution Approach 2:
Different voltage levels are applied to different parts of the circuit - the first transistor operates with a higher voltage (first voltage level) while the second transistor operates with a lower voltage (second voltage level). This local quality differentiation allows each transistor to be optimized for its specific function, reducing power consumption while maintaining fast switching performance
2Speed
If transistor driving performance is increased to shorten output signal fall time, then fall time is reduced, but circuit area increases
Solution Approach 1:
The buffer circuit functionality is segmented into two transistors with different voltage operating points. This segmentation allows each transistor to be smaller in size since they don't need to handle the full voltage swing individually, reducing total circuit area while maintaining fast fall time through coordinated operation
Solution Approach 2:
The circuit uses different voltage parameters (first voltage and second voltage) for the two transistors, where the second voltage is lower than the first voltage. This parameter change allows the second transistor to operate with reduced voltage stress, enabling smaller device dimensions while still achieving rapid discharge and short fall time
Data Source
Figure 1
Figure 2(A)~2(E)
Figure 3
AI summary
A buffer circuit driving method for driving a buffer circuit including: an output terminal (26); a first transistor (21) connected to a signal source (23) of a clock signal that is of at least a first voltage or a second voltage lower than the first voltage, for supplying the first voltage to the output terminal (26); and a second transistor (22) connected to a voltage source (27) that supplies a third voltage lower than the first voltage, for supplying the third voltage to the output terminal (26), includes: causing the first transistor (21) to switch to a conducting state in a period (C) where the clock signal is of the first voltage; and causing the first transistor (21) and the second transistor (22) to switch to the conducting state in a period where the clock signal is of the second voltage, following the period (C) where the clock signal is of the first voltage.