Neuromorphic Computing With Reference Arrays for Drift-Stable Inference
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Solution Overview
Problem
Neuromorphic computing devices using resistive memory cells face accuracy issues due to temperature and time dependency, leading to decreased inference performance.
Innovation Solution
Incorporating a second memory cell array with reference resistive memory cells arranged in columns to generate reference currents, which are used for analog-to-digital conversion of read currents from the first memory cell array, thereby reducing temperature and time dependency effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If resistive memory cells are used for neuromorphic computing, then computational efficiency is improved, but accuracy of inference deteriorates due to temperature and time dependency
Solution Approach 1:
The patent creates a copy of the resistive memory cell characteristics by using a reference memory cell array with identical structure and materials. This reference array copies the temperature and time dependency behavior, allowing the system to measure and compensate for drift effects, thereby maintaining inference accuracy while preserving computational efficiency.
Solution Approach 2:
The patent implements a feedback mechanism where the reference memory cell array continuously monitors the drift effects experienced by the main memory cell array. By comparing read currents from both arrays and adjusting the reference currents accordingly, the system compensates for temperature and time dependency, preventing accuracy degradation.
2Measurement precision
If reference memory cell array is added for compensation, then accuracy of inference is improved, but device complexity increases
Solution Approach 1:
The patent uses reference memory cells with identical structure, materials, and configuration to the main memory cells. This homogeneity ensures that both arrays experience the same temperature and time dependency effects, making the compensation mechanism effective while keeping the added complexity minimal and systematic.
Solution Approach 2:
The patent divides the memory system into two separate but identical arrays: a main memory cell array for computation and a reference memory cell array for compensation. This segmentation allows independent optimization of each array's function while maintaining overall system accuracy, managing complexity through functional separation.
3Reliability
If reference currents are generated by averaging column currents, then temperature and time dependency effects are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent combines multiple column currents from the reference memory cell array through averaging to generate a single reference current. This merging process integrates the characteristics of multiple memory cells, canceling out individual variations and providing a more stable reference current that reduces sensitivity to manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the accuracy and reliability of neuromorphic computing by stabilizing resistive memory cell performance across varying temperatures and times, improving computational precision.
Implementation Method 1
a first memory cell array including a plurality of resistive memory cells that are connected to a plurality of wordlines, a plurality of bitlines and a plurality of source lines, and configured to store data and generate a plurality of read currents based on a plurality of input signals and the data
Implementation Method 2
a second memory cell array including a plurality of reference resistive memory cells that are connected to a plurality of reference wordlines, a plurality of reference bitlines and a plurality of reference source lines, and configured to generate a plurality of reference currents
Data Source
AI summary
A neuromorphic computing device a method of controlling thereof are provided. The neuromorphic computing device includes a first memory cell array including resistive memory cells that are connected to wordlines, bitlines and source lines, and configured to store data and generate read currents based on input signals and the data; a second memory cell array including reference resistive memory cells that are connected to reference wordlines, reference bitlines and reference source lines, and configured to generate reference currents; and an analog-to-digital converting circuit configured to convert the read currents into digital signals based on the reference currents, wherein a voltage is applied to the reference wordlines, the reference resistive memory cells are arranged in columns to form reference columns, and the reference columns are configured to generate column currents, and one of the reference currents is generated by averaging at least two of the column currents.