Semiconductor Memory Power Wiring with Shared iRDL Via Layout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory devices require dedicated areas for routing iRDL vias, leading to increased chip size and power consumption due to the need for exclusive routing regions.
Innovation Solution
The proposed solution involves routing iRDL vias in device locations that lack certain metal layer wirings, allowing the iRDL via routing area to coexist with other device components, thereby eliminating the need for dedicated iRDL layout regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated areas are used for routing iRDL vias, then interference with control signals and wiring is avoided, but chip size increases
Solution Approach 1:
The patent merges the iRDL via routing function with existing via regions used for other purposes (such as memory cell vias or signal vias). By combining multiple functions into the same physical region, the dedicated iRDL via region is eliminated, reducing chip area while maintaining signal integrity through proper via placement and isolation design.
Solution Approach 2:
The patent makes via regions universal by allowing them to serve multiple functions: routing iRDL vias for power distribution, routing signal vias, and providing isolation regions. This multi-functionality eliminates the need for exclusive iRDL via regions, thereby reducing chip size while maintaining reliability.
2Reliability
If dedicated areas are used for routing iRDL vias, then wiring interference is avoided, but power consumption increases
Solution Approach 1:
The patent combines iRDL via routing with existing via regions, eliminating the need for separate dedicated regions. This integration reduces the overall via count and associated parasitic effects, thereby reducing power consumption while maintaining wiring isolation through careful design of the shared via regions.
Solution Approach 2:
By making via regions universal and multi-functional, the patent reduces the total number of vias needed in the device. Fewer vias mean reduced parasitic resistance and capacitance, leading to lower power consumption while maintaining adequate isolation through strategic placement and design of the shared via regions.
3Power
If power is transmitted through lower metal layers, then power distribution is achieved, but power dissipation and heat generation increase
Solution Approach 1:
The patent utilizes the vertical dimension by routing iRDL vias through strategically selected regions that provide optimal conductive pathways. By carefully selecting via locations and utilizing multiple metal layers with appropriate via configurations, the patent creates efficient three-dimensional power distribution networks that reduce current density and associated power dissipation in lower layers.
Solution Approach 2:
The patent changes the physical parameters of power distribution by utilizing iRDL layers with lower resistivity and optimizing via dimensions, materials, and configurations. These parameter changes reduce the overall resistance of power distribution paths, thereby reducing power dissipation and heat generation while maintaining effective power distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip size and power consumption by integrating iRDL via routing with other components, enhancing the efficiency of power supply wiring in semiconductor devices.
Implementation Method 1
an iRDL via provides a conductive pathway between a metal 4 layer and a metal 3 layer
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.