Ferroelectric NAND Memory Cell Layout for Higher Read Margin

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Solution Overview

Problem

Traditional NAND-type memory using ferroelectric field effect transistors (FeFETs) faces challenges due to high variability in ferroelectric material grain/domains, leading to small read margins and high IR drop, which results in low read/program speed.

Innovation Solution

The implementation of a memory device with a ferroelectric based configuration that includes a first transistor (FeFET) and a second transistor sharing gate, source, and drain terminals, along with a ferroelectric capacitor, to enhance current flow and access speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional FeFET-based NAND memory is used, then the device structure is simple, but the read margin is small due to high variability from ferroelectric material grain/domains

Engineering Contradiction:

Improveread marginVSAvoiddevice structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges two transistors (FeFET and second transistor) into a single memory cell structure where they share gate, source, and drain terminals. This combination allows the second transistor to provide additional current flow path that compensates for the high variability in FeFET, thereby improving read margin while maintaining a relatively compact device structure.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The second transistor serves multiple functions: it provides an additional current path to improve read margin, assists in data retention by maintaining voltage levels, and participates in both read and program operations. This multi-functionality addresses the reliability issue without proportionally increasing device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Speed

If traditional FeFET-based NAND memory is used, then the device structure is simple, but the IR drop is very high which causes low read/program speed

Engineering Contradiction:

Improveread/program speedVSAvoidIR drop

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

By merging the FeFET with a second transistor in a shared terminal configuration, the patent creates parallel current flow paths that reduce the overall resistance of the memory cell. This reduces IR drop and enables faster read and program operations compared to traditional single-transistor FeFET structures.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The second transistor acts as an intermediary element that facilitates current flow between the FeFET and the bit line. It provides an additional conduction path that mediates the high resistance issue of traditional FeFET, thereby reducing IR drop and improving speed without requiring fundamental changes to the FeFET structure itself.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250063793A1Method of manufacturing semiconductor device and associated memory device

Publication Date: 2025.02.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a substrate including a planar portion and a mesa portion over the planar portion; an oxide layer over the mesa portion; a ferroelectric material strip covering a protruding plane of the oxide layer and exposing a side plane of the oxide layer; and a gate strip over the ferroelectric material strip and overlapping the oxide layer.