Distance-Based Y Select Pulse Widths for Word Line Access
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Solution Overview
Problem
Conventional memory devices consume unnecessary waiting time and increase power consumption due to setting response times based on the worst-case scenario for memory cells with varying distances from the sense amplifier, leading to reduced performance.
Innovation Solution
A memory device with an X decoder, Y decoder, sense amplifier, and controller that adjusts the pulse width of Y select signals based on the distance between word lines and the sense amplifier, using pulse width control information derived from address information to optimize access times and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the response time is set based on the worst-case scenario for memory cells, then all memory cells can be read and accessed correctly, but unnecessary waiting time is consumed and power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating access time requirements based on the specific location of memory cells relative to the sense amplifier. Memory cells are divided into groups according to their distance from the sense amplifier, with closer cells receiving shorter access times and farther cells receiving longer access times. This localized differentiation ensures reliable access for all cells while eliminating unnecessary waiting time for cells that can be accessed faster.
Solution Approach 2:
The patent implements dynamics by making the access time parameter variable rather than fixed. The controller dynamically adjusts the access time based on the selected memory cell's position, using address information to determine which time parameter to apply. This dynamic adaptation allows the system to optimize performance for each specific access operation while maintaining reliability.
2Reliability
If the response time is set based on the worst-case scenario, then all memory cells can be accessed correctly, but power consumption increases due to unnecessary waiting time
Solution Approach 1:
The patent applies local quality by differentiating power consumption characteristics based on memory cell location. By grouping cells according to their distance from the sense amplifier and assigning different access times to each group, the system reduces unnecessary waiting time and associated power consumption for cells that can be accessed faster, while ensuring adequate time for cells requiring longer access.
Solution Approach 2:
The patent implements dynamics by making the access time parameter variable rather than fixed. The controller dynamically adjusts the access time based on the selected memory cell's position, using address information to determine which time parameter to apply. This dynamic adaptation allows the system to optimize performance for each specific access operation while maintaining reliability.
3Device complexity
If a fixed access time is used for all memory cells, then the system is simple to implement, but performance is reduced due to unnecessary waiting time for fast-response cells
Solution Approach 1:
The patent applies segmentation by dividing the memory cell array into multiple groups based on their distance from the sense amplifier. Each group is assigned a specific access time parameter, creating segmented time management. This segmentation approach balances complexity and performance by using address information to determine which segment a cell belongs to, rather than implementing a fully dynamic continuous adjustment system.
Solution Approach 2:
The patent applies local quality by differentiating access time requirements based on the specific location of memory cells relative to the sense amplifier. Memory cells are divided into groups according to their distance from the sense amplifier, with closer cells receiving shorter access times and farther cells receiving longer access times. This localized differentiation ensures reliable access for all cells while eliminating unnecessary waiting time for cells that can be accessed faster.
Data Source
AI summary
A memory device and a word line signal generating method thereof are provided. The memory device includes a memory cell array, an X decoder, a Y decoder, a sense amplifier and a controller. The word line signal decoder provides a plurality of word line signals on word lines, respectively. The Y decoder respectively adjusts pulse widths of one or more Y select signals according to at least one pulse width control information. The controller generates each of the pulse width control information according to at least one bit of address information of each of the word lines. Wherein, a pulse width of each of the Y select signals is positive correlated to a distance between each of the word lines and the sense amplifier.


