SRAM Layout Pattern With J-Shaped Gates for Exposure Quality
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SRAM architectures face challenges in producing desirable patterns as the gap of the exposure process decreases, leading to issues with exposure quality and transistor performance.
Innovation Solution
The method involves forming a layout pattern of SRAM by creating fin structures and gate structures on a substrate, where the gate structures span the fin structures to form various transistors, including pull-up and pull-down transistors. The gate structures are designed with a curved shape, specifically a J-shaped structure, to optimize space utilization and reduce stress unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional SRAM architecture is used, then manufacturing process is simple, but exposure quality deteriorates as exposure gap decreases
Solution Approach 1:
The gate structure is designed with a curved shape instead of a straight line, forming a J-shaped or L-shaped configuration that spans across the fin structures. This curvature allows the gate to effectively cover the active transistor regions while optimizing the exposure pattern formation, thereby improving exposure quality without requiring additional manufacturing processes.
Solution Approach 2:
The gate structure transitions from a one-dimensional linear arrangement to a two-dimensional curved configuration. By extending the gate in a curved path across multiple fin structures, the design optimizes the spatial distribution of the transistor gates, improving exposure quality through better pattern definition in the photolithography process.
2Reliability
If gate structures span multiple fin structures, then transistor performance improves, but area utilization becomes challenging
Solution Approach 1:
The curved gate structure allows for more efficient packing of transistor gates within the SRAM cell. By using a J-shaped or L-shaped gate configuration, the design maximizes the utilization of available space while maintaining the necessary gate span across fin structures, thereby improving area utilization without compromising transistor performance.
Solution Approach 2:
Multiple gate functions are merged into a single continuous curved gate structure. Instead of having separate straight gates for different transistors, the curved gate structure serves multiple transistors simultaneously, reducing the total area required while maintaining the electrical performance needed for reliable transistor operation.
3Manufacturing precision
If additional processes are added to improve exposure quality, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The curved gate structure is designed to be formed using standard photolithography processes without requiring additional manufacturing steps. The J-shaped or L-shaped configuration is achieved through conventional patterning techniques, thereby improving exposure quality while maintaining manufacturing simplicity and avoiding increased device complexity.
Data Source
AI summary
The present invention provides a method for forming a layout pattern of static random access memory, comprising forming a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PD1A (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PG1A (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) located on the substrate. The PD1A and the PD1B are connected in parallel with each other, the PD2A and the PD2B are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.