Fine-Grained DRAM Dual-Mode I/O for Lower Regular Access Latency
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Solution Overview
Problem
Fine-grained DRAM architectures, while improving memory-level parallelism and reducing activation energy, incur increased access latency due to narrower interfaces, which is detrimental for latency-sensitive regular access workloads.
Innovation Solution
A dual-mode I/O circuit is implemented in fine-grained DRAM memory banks, allowing commands to be routed individually to each grain or fulfilled in parallel by multiple grains, using multi-cast column-address-strobe commands to enhance data width and reduce latency overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If fine-grained DRAM architecture is used to increase memory-level parallelism and reduce activation energy, then energy efficiency and bandwidth scalability are improved, but access latency increases due to narrower interfaces
Solution Approach 1:
The patent implements dynamic interface width adjustment where the DRAM interface can switch between narrow and wide configurations. When regular access patterns are detected, the interface width is increased to reduce latency. This dynamic adaptation allows the system to maintain fine-grained architecture benefits while optimizing for latency-sensitive workloads when appropriate
Solution Approach 2:
The patent changes the interface width parameter dynamically based on access patterns. By adjusting the interface width from narrow (for fine-grained operations) to wide (for regular access), the system resolves the latency penalty without sacrificing the energy efficiency and parallelism benefits of fine-grained architecture
2Productivity
If fine-grained DRAM architecture is used to scale memory bandwidth, then bandwidth and parallelism are improved, but access latency increases proportionately to the number of grains per bank
Solution Approach 1:
The system dynamically adjusts interface width based on workload characteristics. For bandwidth-intensive regular access workloads, the interface width is expanded to reduce latency proportionately, while maintaining the fine-grained parallelism structure for bandwidth scalability
Solution Approach 2:
The DRAM interface is designed to serve multiple functions: it can operate in narrow mode for fine-grained irregular accesses and in wide mode for regular accesses. This multi-functionality allows the same interface to support both bandwidth scaling and latency optimization depending on the workload
Data Source
AI summary
A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.