Memory Bank Latch Segmentation to Prevent Write Collisions
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Solution Overview
Problem
In memory devices like SRAM, collisions can occur when new address and data information is transmitted from global latches to local latches before previous write operations are complete, leading to increased device cycle time due to extended clock pulses.
Innovation Solution
Implementing local latches in local I/Os and local controllers to hold data and address information independently of global latching clock signals, allowing for controlled data transfer and reduced clock pulse duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new address and data information is transmitted from global latches to local latches before previous write operations are complete, then device throughput is improved, but collisions occur leading to increased device cycle time
Solution Approach 1:
The patent divides the single global latching function into separate global and local latches with independent control. Global latches receive data from external interfaces while local latches serve memory banks, allowing independent timing control of each stage to prevent collisions while maintaining high throughput
Solution Approach 2:
The patent implements dynamic control where local latches can be enabled or disabled independently based on operational needs. This allows the system to optimize timing for different operation types (read vs. write) and prevent collisions by selectively activating local latches only when needed
2Reliability
If clock pulse duration is extended to complete previous write operations, then collision prevention is improved, but device cycle time increases
Solution Approach 1:
By segmenting the latching function into global and local stages with independent clock control, the patent eliminates the need to extend global clock pulses for local operations. Each stage can complete its operation with appropriately timed, shorter pulses, preventing collisions without increasing overall cycle time
Solution Approach 2:
Local latches are positioned to receive data from global latches in advance of memory bank operations. This preliminary action allows data to be prepared and staged locally before write operations begin, enabling collision-free parallel operation and shorter clock pulses
Data Source
AI summary
A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.