Memory Device ECC Scrambling for 4-Bit Pattern Error Correction
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Solution Overview
Problem
Existing DRAM devices face challenges in correcting errors of specific patterns due to structural defects in the memory cell array, which conventional ECC circuits cannot address effectively.
Innovation Solution
The memory device employs an ECC circuit that splits input data into sub-data, performs individual ECC encoding on each sub-data, and applies a data scrambling operation based on the memory cell array structure to generate write data, ensuring that each local sense amplifier stores a 2-bit symbol, thereby enabling correction of specific pattern errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC encoding is performed on input data as a whole, then the ECC circuit structure is simple, but it cannot correct errors of specific patterns caused by structural defects in the memory cell array
Solution Approach 1:
The input data is divided into multiple sub-data groups (e.g., first sub-data and second sub-data), and separate ECC encoding is performed on each sub-data group. This segmentation allows the system to handle specific error patterns more effectively by treating different portions of data independently, thereby improving error correction capability for defects localized in specific memory regions.
Solution Approach 2:
Different ECC encoding schemes or parameters are applied to different sub-data groups based on their specific error characteristics. For example, certain sub-data groups may use stronger error correction codes if they are more susceptible to specific pattern errors, allowing localized optimization of error correction without unnecessarily complicating the entire ECC circuit.
2Reliability
If data is split into sub-data and individual ECC encoding is performed on each sub-data, then specific pattern errors can be corrected, but the ECC circuit complexity increases
Solution Approach 1:
The data is segmented into sub-data groups that correspond to specific memory regions or bit line groups. Each sub-data group undergoes independent ECC encoding, which enables targeted correction of errors specific to those regions while keeping the overall circuit architecture manageable through modular design.
Solution Approach 2:
The patent introduces a new dimension of error correction by applying ECC encoding not just across the entire data set but also across multiple sub-data dimensions simultaneously. This multi-dimensional approach allows specific pattern errors to be corrected by leveraging redundancy in different data groupings without requiring a complete redesign of the ECC circuit.
3Reliability
If data scrambling is performed based on memory cell array structure, then 2-bit symbol errors can be corrected for each sub-data, but the processing time increases
Solution Approach 1:
Data scrambling based on memory cell array structure is performed during the write operation in advance, before the data is actually stored and potentially read. This preliminary scrambling ensures that 2-bit symbol errors can be corrected upon reading without requiring additional processing time during critical read operations, as the error correction capability is already embedded in the scrambled data structure.
Solution Approach 2:
The data scrambling operation is merged with the ECC encoding process, combining multiple functions into a single integrated operation. By performing scrambling and encoding together during the write phase, the patent reduces overall processing time while still achieving the capability to correct 2-bit symbol errors when data is retrieved.
Data Source
AI summary
A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.