Planar Ferroelectric Memory Integration for Low-Voltage Data Retention
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Solution Overview
Problem
Existing memory technologies, such as SRAM and DRAM, are volatile and not suitable for low power and compact computing devices due to high write energy, low density, and high power consumption.
Innovation Solution
The integration of a ferroelectric capacitor with a transistor, using a method that involves forming a first etch stop layer with discontinuities, depositing interlayer dielectrics, and patterning the ferroelectric capacitor stack, allowing for low voltage switching and high density memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory technologies (SRAM, DRAM) are used, then memory capacity and speed are achieved, but power consumption is high and data is lost when power is turned off
Solution Approach 1:
The patent changes the fundamental operating principle from volatile to non-volatile memory by using ferroelectric materials with hysteresis loops, allowing data to be retained without continuous power supply. The ferroelectric capacitor maintains polarization states that represent binary data even when power is removed.
Solution Approach 2:
The patent employs composite material structures including ferroelectric layers combined with conductive oxide electrodes and semiconductor layers. This composite approach enables non-volatile memory functionality while maintaining compatibility with existing semiconductor manufacturing processes.
2Quantity of substance
If memory density is increased, then storage capacity improves, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent divides the memory structure into distinct functional layers including separate ferroelectric capacitor layers, electrode layers, and semiconductor layers. This segmentation allows each layer to be optimized independently and simplifies the manufacturing process by enabling modular fabrication approaches.
Solution Approach 2:
The patent transitions from planar memory structures to three-dimensional stacked architectures, stacking multiple memory cells vertically. This dimensional change significantly increases memory density without proportionally increasing manufacturing complexity, as the vertical stacking can be achieved through sequential deposition processes.
3Use of energy by moving object
If write energy is reduced, then power consumption decreases, but switching speed and reliability may be compromised
Solution Approach 1:
The patent exploits the hysteresis loop characteristics of ferroelectric materials, which provide stable polarization states that can be switched at low energy thresholds. The remnant polarization within the hysteresis loop ensures reliable data retention after switching, maintaining reliability even at reduced write energies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of a high-density, low-voltage, non-volatile memory that can operate efficiently, addressing the limitations of traditional memory technologies.
Implementation Method 1
a ferroelectric (FE) material over the second metal
Data Source
AI summary
Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.