Folded Bit-Line Memory Arrays for High-Density Noise Reduction
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Solution Overview
Problem
Existing memory devices employing open bit-line methods face challenges in achieving high integration due to the inability to apply the twisted bit-line pair method, which results in noise interference affecting adjacent memory cells.
Innovation Solution
The implementation of a memory device with overlapping first and second cell arrays, where bit lines from one array overlap with bit lines from the other array, allowing for electrical connections to memory cells in both arrays, thereby reducing noise interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If open bit-line method is used in memory devices, then device complexity is reduced, but noise interference increases affecting adjacent memory cells
Solution Approach 1:
The patent transitions from a planar bit-line arrangement to a three-dimensional stacked configuration. First and second cell arrays are arranged in different layers, with bit lines extending vertically across layers. This spatial separation in the vertical dimension reduces capacitive coupling and noise interference between adjacent bit lines while maintaining electrical connectivity through vertical bit-line segments.
Solution Approach 2:
The bit-line system is divided into multiple independent segments: first bit lines in the first cell array, second bit lines in the second cell array, and vertical bit-line segments connecting them. This segmentation isolates noise in one segment from affecting other segments, allowing each bit-line pair to operate independently with reduced cross-talk.
2Object-affected harmful factors
If twisted bit-line pair method is used, then noise interference is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Instead of twisting bit lines in the planar direction, the patent uses vertical stacking to achieve bit-line separation. The first and second cell arrays are positioned at different vertical levels, with word lines and bit lines extending through intermediate layers. This vertical arrangement provides noise isolation without requiring complex twisting geometries.
Solution Approach 2:
Intermediate layers, including insulating layers and conductor layers, are introduced between the first and second cell arrays. These intermediary structures facilitate the vertical connection of bit lines while maintaining electrical isolation and mechanical stability, simplifying the manufacturing process compared to direct twisting.
3Quantity of substance
If overlapping cell arrays are used, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves high integration by stacking cell arrays vertically rather than expanding them laterally. Multiple cell arrays are positioned at different vertical levels and connected through shared bit-line structures. This vertical integration multiplies storage capacity without proportionally increasing lateral footprint or alignment complexity.
Solution Approach 2:
The vertical bit-line segments serve multiple functions: they connect first bit lines to second bit lines, provide electrical continuity across layers, and act as signal transmission paths. This multi-functionality reduces the number of separate components needed, lowering manufacturing precision requirements despite the stacked configuration.
Data Source
AI summary
A novel memory device is provided. A first cell array including a plurality of memory cells and a second cell array including a plurality of memory cells are provided to overlap with each other. Two bit lines included in the first bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. Two bit lines included in the second bit line pair are electrically connected to part of the memory cells included in the first cell array and to part of the memory cells included in the second cell array. In the first cell array, one of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair. In the second cell array, the other of the bit lines included in the second bit line pair includes a region overlapping with part of the first bit line pair.