High-Voltage Isolation Layout for 3D NAND Leakage Control
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently isolating high voltage operations from low voltage components, leading to potential leakage currents and increased manufacturing costs due to variability in memory cell performance.
Innovation Solution
The implementation of high voltage isolation devices with narrow active areas and interdigitated gate structures, allowing for precise control of conductivity through gate dielectric materials, effectively couples or decouples memory cells from page buffers based on voltage levels, thereby reducing leakage currents and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional isolation devices are used to separate high voltage and low voltage components, then voltage isolation is achieved, but leakage currents increase and manufacturing variability worsens
Solution Approach 1:
The isolation device is segmented into distinct high voltage and low voltage regions with clearly defined boundaries. The gate structure is divided into separate high voltage gate and low voltage gate portions, each controlling their respective regions independently. This segmentation prevents voltage interference and reduces leakage currents between the high voltage memory cell array and low voltage page buffer circuits.
Solution Approach 2:
Different regions of the isolation device are assigned different doping concentrations and material properties optimized for their specific voltage requirements. The high voltage region uses materials and doping profiles optimized for high voltage operation, while the low voltage region uses configurations optimized for low voltage operation. This local optimization improves overall isolation effectiveness and reduces harmful leakage effects.
2Reliability
If conventional isolation structures are used, then voltage separation is achieved, but manufacturing precision and consistency deteriorate
Solution Approach 1:
The manufacturing process is segmented into separate stages for forming high voltage and low voltage regions, allowing each region to be optimized independently. This segmentation enables precise control over doping concentrations, gate lengths, and other critical dimensions for each voltage domain, improving manufacturing precision and reducing variability in memory cell performance across the device.
Solution Approach 2:
The invention employs different physical and electrical parameters for high voltage and low voltage regions, including different doping concentrations, gate oxide thicknesses, and channel lengths. These parameter changes allow each region to be manufactured with optimized tolerances, improving overall manufacturing precision and consistency of memory cell performance while maintaining effective voltage isolation.
3Reliability
If traditional isolation devices are used, then voltage isolation is provided, but device area increases
Solution Approach 1:
The isolation device merges high voltage and low voltage circuits into a single integrated structure with shared components where possible. The gate dielectric layer and substrate structure are shared between high voltage and low voltage regions, reducing redundant materials and minimizing the overall isolation device area while maintaining effective voltage separation through optimized region boundaries.
Solution Approach 2:
The invention utilizes vertical dimensionality by stacking high voltage and low voltage regions in overlapping configurations where possible. The gate structures extend in multiple dimensions, allowing voltage isolation to be achieved through vertical field effects rather than requiring large lateral separation distances. This dimensional approach significantly reduces the horizontal area occupied by the isolation device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and efficiency of semiconductor memory devices by minimizing leakage currents during high voltage operations and reducing the area occupied by isolation devices, thereby supporting increased memory cell density and reduced manufacturing costs.
Implementation Method 1
gates coupled with the narrow active areas to control conductivities of the narrow active areas through a gate dielectric material
Data Source
AI summary
High voltage isolation devices for semiconductor devices and associated systems, are disclosed herein. The isolation device may support operations of a 3-dimensional NAND memory array of the semiconductor device. In some embodiments, during high voltage operations (e.g., erase operations), the isolation device may provide a high voltage to the memory array while isolating other circuitry supporting low voltage operations of the memory array from the high voltage. The isolation device may include a set of narrow active areas separating the low voltage circuitry from the high voltage and a gate over the narrow active areas. In a further embodiment, the isolation device includes interdigitated narrow active areas and a common gate over the interdigitated narrow active areas to reduce an area occupied by the isolation devices.