MRAM Write-Voltage Calibration With a Mimic Column
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Solution Overview
Problem
Existing MRAM technologies face challenges in supplying sufficient write current due to large resistances along the electrical path, leading to insufficient headroom in power supply voltage and unnecessary power consumption during standby operations, with stability issues arising from varying MTJ resistances.
Innovation Solution
A calibration circuit is implemented with a mimic column that replicates the memory array, using mimic cells to emulate parasitic resistances, allowing for voltage calibration to ensure sufficient current flow during write operations, reducing parasitic impedance, and minimizing power consumption in standby modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large write current is supplied to MRAM cells, then write operation reliability is improved, but power supply voltage headroom is insufficient due to large parasitic resistances
Solution Approach 1:
The patent performs write voltage calibration during a preliminary calibration phase before normal write operations. The calibration circuit determines the actual write voltage at the memory cell location accounting for parasitic resistances, and stores calibration data that is used during subsequent write operations to compensate for voltage drops and ensure sufficient write current.
Solution Approach 2:
The patent introduces a calibration circuit as an intermediary component that measures and characterizes the voltage drop across parasitic resistances. This calibration circuit includes sense amplifiers and control logic that mediate between the write driver and memory cells, enabling accurate determination of write voltage conditions without requiring excessive voltage headroom.
2Reliability
If write voltage is increased to overcome parasitic resistances, then sufficient write current is achieved, but power consumption increases during standby operations
Solution Approach 1:
The patent dynamically adjusts write voltage based on calibration data rather than using a fixed high voltage. The write driver selects from multiple voltage levels (e.g., VWRITE0, VWRITE1, VWRITE2) depending on the calibrated characteristics of specific memory cells, allowing optimal voltage to be applied only when needed for reliable writes while maintaining lower voltages during standby.
Solution Approach 2:
The patent changes the write voltage parameter based on calibrated resistance values and process-temperature-voltage (PTV) conditions. The calibration circuit stores multiple voltage compensation values that are selected during write operations based on actual cell conditions, enabling adaptive voltage adjustment that ensures sufficient write current while minimizing power consumption during non-write operations.
3Device complexity
If fixed write voltage is used, then circuit simplicity is maintained, but write operation stability deteriorates due to varying MTJ resistances
Solution Approach 1:
The patent implements a feedback mechanism where the calibration circuit measures actual write voltage conditions and stores calibration data that reflects the relationship between write voltage and MTJ resistance variations. During write operations, this calibration data provides feedback to the write driver to select appropriate voltage levels, compensating for PTV effects and ensuring stable write operations despite varying MTJ resistances.
Solution Approach 2:
The patent performs preliminary calibration to characterize write voltage conditions across different process corners, temperatures, and MTJ resistance values. This preliminary action creates a lookup table or calibration data structure that guides write voltage selection, eliminating the need for complex real-time adjustments while maintaining stability across varying conditions.
Data Source
AI summary
An example is a circuit. The circuit includes a memory array, a mimic column, a mimic resistor, and a calibration circuit. The mimic column is along a periphery of the memory array. The mimic resistor is in a path through the mimic column. The calibration circuit is configured to calibrate a voltage for writing a memory cell in the memory array. The calibration circuit is electrically connected to the mimic resistor. A voltage may be calibrated, such as by the calibration circuit, using the mimic column. A value may be written to a memory cell of the memory array using the calibrated voltage.