PLD Readback Circuit Using Enable Bits for Error Detection
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Solution Overview
Problem
Conventional approaches for facilitating compatibility between allocating distributed RAM and performing error detection in programmable logic devices require additional circuitry for each memory cell, leading to increased transistor count and device area, making it necessary to provide improved ways for deterministic read back and error detection.
Innovation Solution
The solution involves using a distributed RAM enable bit stored in configuration memory to determine whether memory cells are used for configuration data or non-configuration data, allowing for deterministic read back without additional circuitry on a cell-by-cell basis, and utilizing an address logic circuit and read back circuit to selectively provide data bit values based on the enable bit's state, reducing the number of components and die space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuitry is added for each memory cell to block read out during error detection, then error detection compatibility is improved, but transistor count and device area increase significantly
Solution Approach 1:
The configuration memory is segmented into two distinct types of memory cells: distributed RAM cells and non-distributed RAM cells. Each type is independently controllable through type indication bits, allowing selective read-back of only the non-distributed cells for error detection while leaving distributed cells available for data storage. This segmentation eliminates the need for additional blocking circuitry in each cell since the error detection process naturally targets only the appropriate cell type.
Solution Approach 2:
The patent performs preliminary classification of memory cells into distributed and non-distributed types during the configuration phase, storing type indication bits alongside each cell's data. This preliminary action enables the error detection mechanism to identify and read-back only the non-distributed cells without requiring runtime decision-making or additional blocking circuitry, thereby reducing device complexity while maintaining error detection capability.
2Adaptability or versatility
If configuration memory is allocated for distributed RAM to store user data, then memory utilization is improved, but error detection accuracy deteriorates due to non-predetermined values
Solution Approach 1:
The memory system is segmented into distributed RAM cells (for user data) and non-distributed RAM cells (for configuration data). Type indication bits are stored with each cell to identify its function. During error detection, only non-distributed cells are read-back and compared with original configuration data, while distributed cells remain dedicated to user data storage. This segmentation allows both high memory utilization and accurate error detection to coexist without interference.
Solution Approach 2:
Type indication bits serve as intermediaries that carry metadata about each memory cell's intended use. These bits enable the error detection mechanism to distinguish between distributed and non-distributed cells, allowing the system to selectively process only the appropriate cells for error checking while maintaining full functionality of both memory types.
3Adaptability or versatility
If conventional error detection methods are used with distributed RAM allocation, then compatibility between error detection and distributed RAM is improved, but additional circuitry requirements increase device complexity
Solution Approach 1:
The patent segments the configuration memory into distributed and non-distributed cell types, with each type having dedicated read-back pathways controlled by type indication bits. This segmentation enables conventional error detection methods to be applied to non-distributed cells without requiring any distributed RAM cells to be blocked or prevented from read-out, achieving full compatibility while avoiding additional blocking circuitry.
Solution Approach 2:
The type indication bits embedded with each memory cell enable the memory system to self-identify and self-select which cells should undergo error detection. This self-service mechanism eliminates the need for external control logic or additional circuitry to manage the interaction between distributed RAM allocation and error detection, reducing device complexity while maintaining compatibility.
Data Source
AI summary
Various techniques are provided to efficiently implement deterministic read back and error detection for programmable logic devices (PLDs). In one example, a PLD includes an array of memory cells arranged in rows and columns, where at least one row includes an enable bit. The PLD further includes an address logic circuit configured to selectively assert the columns of the array by respective address lines. The PLD further includes a register configured to store a value of the enable bit in response to an assertion of an address line corresponding to the enable bit. The PLD further includes a read back circuit configured to selectively provide, for each memory cell, a data bit value stored by the memory cell or a predetermined data bit value based at least on the stored value of the register. Additional systems and related methods are provided.