Vertical 2T Memory Cell Shielding for Leakage and Coupling
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Solution Overview
Problem
Conventional volatile memory devices face challenges in increasing storage density due to physical limitations and fabrication constraints, leading to excessive capacitive coupling between adjacent memory cells and requiring high threshold voltages for transistors.
Innovation Solution
The memory device incorporates a 2T memory cell structure with a single access line to control two transistors, a cross-point gain cell structure for efficient operation, and a conductive shield structure to prevent current leakage and reduce capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is shrunk to increase storage density, then device storage density is improved, but excessive capacitive coupling occurs between adjacent memory cells
Solution Approach 1:
A conductive shield structure is introduced as an intermediary element positioned between adjacent memory cells. This shield structure acts as a mediator that blocks or reduces the capacitive coupling between neighboring cells, allowing high storage density to be achieved without suffering from excessive interference between closely spaced cells.
Solution Approach 2:
The harmful capacitive coupling effect is extracted and isolated by introducing a separate conductive shield structure. This shield structure specifically targets and mitigates the capacitive coupling issue without requiring changes to the core memory cell design, allowing the memory cells to maintain their high-density configuration.
2Quantity of substance
If memory cell size is shrunk to increase storage density, then device storage density is improved, but physical limitations and fabrication constraints are encountered
Solution Approach 1:
The memory cell structure transitions to a vertical configuration where transistors are stacked above each other rather than arranged horizontally. This dimensional change allows storage density to increase vertically without requiring further horizontal shrinkage, thereby avoiding the physical and fabrication limitations that would result from continuing to reduce lateral dimensions.
Solution Approach 2:
Multiple functional elements (transistors, charge storage structures, access lines) are merged into a compact vertical stack within the memory cell. This integration reduces the overall footprint of each memory cell and simplifies the fabrication process by allowing simultaneous formation of multiple components through stacked processing techniques.
3Reliability
If conventional memory cell structure is used, then information storage is achieved, but current leakage occurs reducing retention
Solution Approach 1:
The conductive shield structure serves as an intermediary that blocks leakage current paths between adjacent memory cells. By positioning the shield between cells, it prevents charge from leaking across cell boundaries, thereby improving information retention without affecting the core storage mechanism.
Solution Approach 2:
The conductive shield structure is positioned in advance to prevent potential current leakage before it can occur. By having the shield structure already in place between adjacent cells, any leakage current that might otherwise flow between cells is blocked proactively, ensuring reliable information retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a smaller memory device footprint, reduced power dissipation, improved processing efficiency, and enhanced retention of stored information by mitigating leakage and capacitive coupling issues.
Implementation Method 1
The conductive shield structure can suppress or prevent potential leakage of current in the memory cell
Implementation Method 2
Most conventional volatile memory devices store information in the form of charge in a capacitor structure included in the memory cell
Data Source
AI summary
Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.