Shielded Clock Signal Lines for Stable Multiphase Memory Timing
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Solution Overview
Problem
Semiconductor memories face issues with timing deviations in clock signals, which can lead to erroneous operations, especially at higher frequencies, due to varying voltage conditions, affecting the proper functioning of internal circuits.
Innovation Solution
The implementation of a clock dividing circuit that generates multiphase clock signals with controlled phase and frequency, along with electrical shielding using conductive lines to maintain consistent voltage conditions for the clock signals, mitigates timing deviations and ensures stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to improve memory speed, then productivity is improved, but timing deviation increases causing erroneous operation
Solution Approach 1:
A shield circuit is introduced as an intermediary element disposed between signal lines carrying clock signals. The shield circuit provides a controlled voltage environment that mediates the electromagnetic interference between adjacent clock signal lines, thereby maintaining timing accuracy even at high clock frequencies.
Solution Approach 2:
The shield circuit dynamically adjusts the voltage parameter of the conductive lines between clock signal lines. By changing the voltage state of the shield (e.g., switching between VDD and VSS based on detected clock edges), the circuit compensates for voltage-induced timing deviations and maintains consistent clock signal propagation.
2Device complexity
If voltage conditions vary for internal clock signals, then device complexity is reduced, but timing deviation occurs causing erroneous operation
Solution Approach 1:
The shield circuit incorporates a feedback mechanism that detects clock signal edges and responds by adjusting the shield voltage accordingly. This feedback loop ensures that voltage conditions are actively maintained to prevent timing deviations without requiring complex external voltage control circuitry.
Solution Approach 2:
The shield circuit operates autonomously by detecting clock edges and self-adjusting its voltage state without external intervention. This self-service capability maintains reliable clock timing while keeping the overall device complexity low, as the shield circuit handles voltage compensation internally.
Data Source
AI summary
Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.