Analog In-Memory Neural Compute With Reference Cell PVT Stabilization
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Solution Overview
Problem
Current neural network hardware accelerators face challenges in achieving high-performance compute operations while minimizing energy consumption, limiting their applications and efficiency.
Innovation Solution
The system employs an array of neurons with a gate-drain connected flash cell configuration, operational amplifiers, and analog to digital converters to perform in-memory compute operations, where neurons receive pulses generating currents proportional to inputs, and a reference cell maintains a threshold voltage to stabilize operations across PVT variations, enabling efficient charge management and low energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If CPU's and GPU's are used to implement neural network models, then compute operations can be performed, but power consumption is high and performance is limited
Solution Approach 1:
The patent replaces traditional digital computing systems (CPU/GPU) with an analog in-memory computing system that performs neural network operations directly in the memory array. This substitution of the computing paradigm enables simultaneous improvement in power consumption and compute performance by eliminating data movement between separate memory and processing units.
Solution Approach 2:
The patent merges memory and computing functions into a single integrated system where the memory array simultaneously stores weights and performs multiply-accumulate operations. This merging eliminates the memory wall bottleneck and reduces power consumption associated with data transfer, while maintaining high compute throughput.
2Adaptability or versatility
If traditional digital computing is used for neural networks, then applications can be implemented, but energy efficiency is poor
Solution Approach 1:
The patent changes the fundamental operating parameters from digital to analog domain, enabling neural network computations to be performed with continuous voltage levels. This parameter change allows the system to achieve high energy efficiency while maintaining the ability to implement various neural network applications through programmable weight configurations.
3Use of energy by moving object
If analog in-memory compute is implemented, then power consumption is reduced, but stability across PVT variations must be maintained
Solution Approach 1:
The patent implements feedback mechanisms through reference cells that generate control gate voltages to compensate for process, voltage, and temperature variations. The reference cells provide real-time calibration signals that adjust the operating point of the memory array, maintaining computational accuracy despite PVT variations while preserving low power consumption.
Solution Approach 2:
The patent uses reference cells to establish equipotential conditions across the memory array by generating control voltages that equalize the operating conditions of different memory cells. This approach ensures uniform response characteristics across the array, improving reliability without increasing power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-performance neural network computations with significantly reduced power consumption, expanding the scope of applications that can benefit from neural networks by optimizing energy usage and stability.
Implementation Method 1
Each neuron of the array of neurons receives a pulse of magnitude xi, and duration t, wherein a product xi*yi provides a current proportional to the input for a time duration t, which is a charge associated with a particular neuron
Implementation Method 2
a voltage is created at a drain of the reference cell, and wherein the voltage is then buffered with an operational amplifier that generates a control gate voltage VCG
Implementation Method 3
the sense node is used to sense the total charge discharged through the bit line of the neural array over a predetermined amount of time
Data Source
AI summary
In one aspect, a system for analog in-memory compute for a neural network includes an array of neurons. Each neuron of the array of neurons receives a pulse of magnitude xi, and duration t, wherein a product xi*yi provides a current proportional to the input for a time duration t, which is a charge associated with a particular neuron in response to the input being presented to that particular neuron. A reference cell includes a gate-drain connected flash cell configuration and coupled with the array of neurons. The reference cell is programmed to a pre-determined threshold voltage Vt-ref. The reference cell receives a pre-determined current, Iref, wherein, based on the Iref and a pre-determined threshold voltage Vt-ref, a voltage is created at a drain of the reference cell.