Dual-Array Memory Programming for ISPP Speed-Reliability Tradeoff
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Solution Overview
Problem
The trade-off between incremental step pulse programming (ISPP) step size and reliability affects the output voltages of memory devices, impacting their operational reliability.
Innovation Solution
The memory device is divided into two arrays, with one array performing ISPP in a higher voltage step for temporary data storage and another in a lower voltage step for long-term storage, allowing different step sizes for improved efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a larger ISPP step size is used, then programming speed is improved, but output voltage distribution and reliability deteriorate
Solution Approach 1:
The memory array is divided into two separate arrays: a first array for temporary data storage and a second array for final data storage. This segmentation allows each array to use different ISPP step sizes optimized for its specific function, resolving the contradiction between speed and reliability.
Solution Approach 2:
Different ISPP step sizes are applied to different arrays based on their specific functions. The first array uses a first ISPP step size optimized for temporary storage operations, while the second array uses a second ISPP step size optimized for final storage and reliability, allowing local optimization of voltage parameters.
2Reliability
If a smaller ISPP step size is used, then reliability is improved, but programming speed deteriorates
Solution Approach 1:
The memory system is segmented into two arrays with different programming characteristics. The first array can use larger ISPP step sizes for faster temporary storage, while the second array uses smaller ISPP step sizes for reliable final storage, thus maintaining both speed and reliability in their respective operations.
Solution Approach 2:
Data is first temporarily stored in the first array using optimized ISPP parameters for speed, then transferred to the second array for final storage with optimized ISPP parameters for reliability. This preliminary action in the first array enables overall system efficiency while ensuring final data integrity.
Data Source
AI summary
A memory device comprising a memory array, a voltage generator and an array control circuit is provided. The memory array is coupled to the voltage generator and comprises first and second arrays. The array control circuit is coupled to the memory array and the voltage generator, and configured to: in a programming stage, control the voltage generator to generate a first control voltage, and generate a temporary address to control the first array to store storage data and address data in a first programming step according to the temporary address and the first control voltage; in an idle stage, control the voltage generator to generate a second control voltage, and control the second array to store storage data in a second programming step according to address data and the second control voltage. The voltage of the first programming step is greater than the voltage of the second programming step.