Anti-Ferroelectric Gate Stack for Low-Voltage Domain Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing silicon-based transistors face limitations in reducing operating voltage below 0.8 V, leading to increased power density and potential device failure due to heat generation, making it challenging to scale down devices effectively.
Innovation Solution
A domain switching device is developed with a channel region, source and drain, a gate electrode isolated from the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region, which enables low operating voltage and improved control efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of transistor is decreased to enable scaling down, then device distribution density is increased, but power density increases and heat generation causes device failure
Solution Approach 1:
The patent changes the material parameter of the gate insulator from conventional silicon oxide to anti-ferroelectric material (such as HfO2, Pb(Zr,Ti)O3), which fundamentally alters the electrical characteristics and enables lower operating voltages, thereby reducing power density and heat generation in scaled-down devices
Solution Approach 2:
The patent employs composite material structures including anti-ferroelectric layers combined with conductive layers (such as RuO2, IrO2) and barrier layers, creating a multi-layer gate stack that achieves both low operating voltage and high reliability in miniaturized transistors
2Use of energy by moving object
If operating voltage is reduced below 0.8 V to improve power efficiency, then power density decreases, but existing silicon-based transistors cannot achieve this voltage level
Solution Approach 1:
The patent utilizes the phase transition characteristics of anti-ferroelectric materials, which can switch between ferroelectric and anti-ferroelectric phases, enabling precise control of electric field and achieving operating voltages below 0.8 V while maintaining device functionality
Solution Approach 2:
The anti-ferroelectric gate insulator structure serves multiple functions simultaneously: it provides high breakdown voltage for low operating voltage operation, enables field effect control, and maintains thermal stability, making it universally applicable to various transistor configurations
3Productivity
If distribution density of device is increased to improve integration, then more devices can be packed, but heat generation increases causing device failure
Solution Approach 1:
The patent changes the electrical parameter of the gate insulator to anti-ferroelectric material with higher dielectric constant and breakdown voltage, enabling lower operating voltages that directly reduce power consumption and heat generation, thereby allowing higher device distribution density without thermal failure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The domain switching device achieves improved subthreshold swing (SS) values and enhanced control efficiency, facilitating device scaling down while reducing the risk of heat-induced failure.
Implementation Method 1
an anti-ferroelectric layer between the channel region and the gate electrode
Implementation Method 2
a conductive layer between the gate electrode and the anti-ferroelectric layer, the conductive layer in contact with the anti-ferroelectric layer
Implementation Method 3
a barrier layer between the anti-ferroelectric layer and the channel region
Data Source
AI summary
A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.