3D 2T1C Semiconductor Memory Cell Structure for Dense Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The degree of integration of two-dimensional semiconductor memory devices is limited by the area occupied by unit memory cells, hindering the development of miniaturized, multi-functional, and high-performance high-capacity memory devices.
Innovation Solution
A three-dimensional (3D) two-transistor-one-capacitor (2T1C) semiconductor memory device design featuring a specific arrangement of write and read transistors, bit lines, word lines, and capacitors, including a capacitor electrode with distinct portions and dielectric layers, allowing for vertical stacking of memory cells and reduced capacitor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices are used, then the device area is limited, but the degree of integration is still limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional vertical stacking. Multiple memory cells are stacked in the vertical direction (third dimension) to increase memory capacity without proportionally increasing the planar device area. This dimensional change allows higher integration density by utilizing the vertical space for additional memory cells.
2Quantity of substance
If capacitor size is reduced for vertical stacking, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
The capacitor electrode is divided into multiple discrete portions (first portion, second portion, third portion) that are formed at different vertical levels and horizontal positions. This segmentation allows each capacitor portion to be fabricated with controlled dimensions and precise positioning, facilitating reduced capacitor size while maintaining manufacturing feasibility through staged formation processes.
Solution Approach 2:
Multiple capacitor portions are nested within the same memory cell structure at different vertical levels. The first, second, and third capacitor portions are integrated into the memory cell in a stacked configuration, allowing compact capacitor implementation that reduces overall capacitor area while maintaining functional integrity through multi-level nesting.
3Quantity of substance
If vertical stacking of memory cells is implemented, then memory capacity increases, but device complexity increases
Solution Approach 1:
The memory cell structure is designed with multi-functional components. The capacitor electrode portions serve both as capacitor elements and as shared word line connections. The gate dielectric layers and channel layers are configured to perform both transistor gating and capacitor electrode functions in certain regions, reducing the number of separate components needed and thereby reducing overall device complexity despite vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances integration and operation reliability while reducing power consumption by enabling a smaller capacitor implementation and efficient data reading through capacitance sensing.
Implementation Method 1
a capacitor dielectric layer arranged between the capacitor electrode and the read word line
Implementation Method 2
a first gate dielectric layer covering a side surface of the first portion of the capacitor electrode; a second gate dielectric layer covering a portion of a side surface of the write word line
Data Source
AI summary
A semiconductor memory device includes a write bit line and a read word line extending in a first horizontal direction and spaced apart from each other in a second horizontal direction, a write word line, a read bit line, and a source line between the write bit line and the read word line and extending in a vertical direction and being spaced apart in the first horizontal direction, a capacitor electrode having a first portion and a second portion, a capacitor dielectric layer, a first gate dielectric layer covering a side surface of the first portion, a first channel layer covering the first gate dielectric layer, a second gate dielectric layer covering a portion of a side surface of the write word line, and a second channel layer connected to the second portion of the capacitor electrode and to the write bit line and covering the second gate dielectric layer.