Digital Storage TRIZ Cases

A series select gate transistor isolates the ferroelectric memory transistor to reduce disturb and improve data retention reliability.

Time-varying in-situ ECC refresh preserves memory read window budget and data retention while limiting capacity, bandwidth, and power overhead.

Alternating asymmetric field recovery cycling restores fatigued FeRAM polarization, preserving multi-bit retention and cell endurance.

A copied current controls a parallel write transistor to stabilize programming current in resistance-change memory cells.

Separate read and write bias standby modes cut memory standby current while keeping read wake-up time low.

A 3D cross-bar thyristor memory uses stair source lines and gate control to simplify read, write, and erase while limiting sneak currents.

Diagonal conductor cells and self-rectifying memristors suppress sneak current for fast, accurate, low-power graph data analysis.

Automatic translation and repetition rules expand storage arrays without boundary or coordinate errors, improving semiconductor layout efficiency and quality.

A fly word line layout uses front- and back-side routing to cut resistance, capacitance, and edge-cell access delays in CFET memory arrays.

Electric-field tuning of the MTJ energy barrier lets magnetic memory switch between low-power non-volatile storage and fast volatile access for edge AI.

Segmented spacer etching with an etch stop preserves top electrode height, keeps the metal-line landing window, and reduces MRAM cell damage.

Position-based dopant concentration in selection element layers equalizes memory cell threshold voltage and stabilizes operation across the cell area.

Charge redistribution with grounded capacitors and feedback op-amps cuts CIM power use while stabilizing bit-line voltages for matrix multiplication.

A delayed clock change after low-power entry prevents synchronization faults when semiconductor devices switch frequency modes.

Varying peripheral cell heights around a memory array improves integration and operation while avoiding a fully uniform, harder-to-build layout.

Shared bit-line SOT MRAM uses a heavy-metal spin-current layer to avoid direct MTJ write current, cutting write errors, energy use, and delay.

Separate precharge signals keep the reference bit line at voltage, reducing noise coupling and extending DRAM sensing time.

Shared data bumps are selectively switched between two memory stacks to improve HBM signal routing and free residual bumps for power.

A two-phase supply ramp pre-charges the read circuit before full sensing to limit bitline coupling and improve non-volatile memory read accuracy.

Per-row activation counting identifies aggressor rows and refreshes queued victim rows to curb DRAM rowhammer bit flips.

Three stacked transistor paths reduce kickback noise and minimum operating voltage, enabling faster and more accurate signal sensing.

Alternating word lines isolate adjacent memory cells to prevent dummy reads, cut power use, and reduce read/write disturbance risk.

Vertical 2T1C cell stacking increases memory density in less area while using segmented capacitor electrodes for reliable, low-power capacitance sensing.

A segmented DRAM bit line with conductive stairs and selection transistors helps prevent manufacturing disconnection and preserve memory performance.

A vertical FeFET layout stacks gate, ferroelectric, and channel layers to raise integration density while limiting interference in scaled memory cells.

An error report circuit lets the host detect in-memory processing faults without returning intermediate data, reducing overhead and wasted calculations.

Segmented data lines and external line-segment multiplexing raise DRAM bandwidth while preserving cell density without dummy columns.

Counts DBI signal bits to choose original or inverted write data, keeping 1s below a set limit to cut memory write power.

Periodic word-line polarity reversal cuts PBTI and NBTI stress in oxide semiconductor DRAM, stabilizing threshold voltage and memory reliability.

Slew-rate control reshapes crossbar input signals to curb parasitic-capacitance disturbance, avoiding unintended RRAM programming and VMM errors.

Bitline base-voltage precharge offsets parasitic capacitance, enabling lower plateline read voltage, wider read window, and less cell stress.

A mixed-drift PCM array lets HD models decay after a set time, enabling secure forgetting with lower power in edge computing.

Adjustable channel widths, bank access, and burst settings help one memory architecture match different controllers and improve transfer efficiency.

Erasure position detection and syndrome matching correct erased ferroelectric memory bits, improving read data integrity despite leakage and fatigue.

Stacked cylindrical electrodes with dielectric and support layers raise 3D DRAM capacitor capacity while using chip space more efficiently.

A dual-voltage regulator separates memory write and read power paths, preserving read access when the high-voltage node is damaged.

Three-transistor MRAM synapse cells isolate unselected array paths to cut read disturb and preserve accurate weight retrieval in larger arrays.

A ferroelectric gate stack and vertical channel structure expand the memory window and speed erase in highly integrated multi-state memory.

Split read and write select transistors cut bit line loading, reducing read delay and energy while preserving write current.

Shared word lines across stacked sub-memory arrays reduce wiring and peripheral circuit area while preserving high memory density.

A horizontal 2T0C memory cell layout removes unstable high-aspect-ratio capacitors, improving DRAM yield, stacking density, and storage capacity.

A doped non-stoichiometric oxide capping layer cuts resistance and blocks oxygen diffusion, preserving STT-MRAM PMA up to 400°C.

A row-based SOT-MRAM matrix uses opposite write currents and sense amplifiers to enable concurrent read-write operation without mode interference.

Gradually raised read voltage keeps ferroelectric polarization intact, avoiding destructive reads, write-back power, and reliability loss.

Targeted host-requested memory refresh estimates timing in advance, cutting read latency and power use while preserving stored data reliability.

A stacked read/write DRAM cell uses a vertical tunneling FET to curb leakage current, enabling smaller cells and longer retention time.

Delaying plate voltage relative to the digit line during memory sensing reduces voltage offset disturb and improves FeRAM reliability.

Block-level activation counters trigger local and adjacent DRAM refreshes to contain row hammering beyond matrix boundaries.

Adaptive offset compensation timing and voltage control help DRAM sense amplifiers maintain sensing margin under PVT-driven offset noise.

Delayed precharge test timing exposes word line driver defects in memory mats, improving read and write reliability.

A comparator monitors RRAM resistance trends to optimize write operations.

An inverter circuit conditions control signals to maintain transistor states, preventing spurious writes caused by negative voltage spikes.

A master chip controls internal voltage levels of slave chips to synchronize signal phases across stacked semiconductor layers.

Segmented word lines with a compensation driver recycle bit line charges to reduce RC delays and voltage drops in SRAM arrays.

An enable circuit manages PMOS power switches in SRAM memory devices to reduce bulk-to-source leakage currents during shutdown operations.

A develop reference voltage generator adjusts output based on transistor threshold characteristics to stabilize sense amplifier operation.

Segmented local and global bitlines reduce capacitance and eliminate data pattern-dependent voltage drops during early masked writes.

A 7T memory cell varies power supply voltages during write operations to reduce energy consumption.

Counter circuitry verifies row refresh completion to lower frequency, reducing power consumption while maintaining data reliability.

A DRAM controller adjusts clock phase to synchronize control signals.

Control unit generates signals to buffers that pass original or inverted data to memory cells for simultaneous testing.

Column read BIST modes exercise all transistors via search lines, reducing test time and cost while maintaining thorough memory cell coverage.

Strategic well strap cells reduce inter-diffusion counter-dope effects to improve latch-up immunity without increasing array area.

A single static source line merges bit and source tracks to reduce STRAM cell width, balancing write currents while resolving asymmetric current challenges.

Auxiliary current from VDD maintains core voltage stability during precharge, preventing errors caused by excessive current consumption.

A memory module with optical interconnect uses a buffer to handle requests via an optical channel, enabling high-speed serial links without consuming many pins.

Step-down voltages and back bias minimize leakage in HBM wiring.

Jointly calibrating reference voltage and equalizer coefficients maximizes eye diagram width, resolving complexity in DRAM receiver optimization.

Segmented sub-drivers reduce wire load and power loss while maintaining high data processing speeds in three-dimensional memory stacks.

An inductor and NMOS transistors store discharged charges at an intermediate voltage to reduce dynamic power consumption.

A dual rail power switch disconnects core logic circuitry from a lower voltage rail using a higher gate voltage level to minimize leakage current.

Auxiliary line pairs drive parasitic capacitance to generate negative bias, reducing power consumption and area of write assist circuits.

A clock-independent mode register setting apparatus uses a data strobe signal to initiate memory configuration operations.

Vertical stacking of ferroelectric transistors increases density while reducing read latency and power dissipation.

Shorter pulse width write clock signals reduce word line activation duration, minimizing unwanted current flows and power consumption in SRAMs.

A controller adjusts on-die termination duration to synchronize memory modules.

A decoded interval range TCAM separates search bits into groups to reduce silicon area.

Opposite polarity charging pulses protect tunnel barriers in spin-torque magnetic random access memory cells.

Iterative per-bit de-skew calibration resolves signal integrity bottlenecks by adjusting delay values for datamask lines relative to data strobe timing.

A driving method applies specific voltage pulses to a segmented metal oxide layer to change resistance states in non-volatile memory devices.

A vertical decoder uses doped materials extending perpendicular to a substrate to couple conductive lines with memory cell access lines.

A quasi-feedback level shifter circuit manages voltage translation between VDD and VCS domains using unselected inputs to break feedback loops.

A liner layer contacts adjacent memory cells to reduce heat loss, mitigating thermal disturbance in highly integrated semiconductor devices.

Canary circuits predict partial breakdown of memory bitcells through controlled stress application, preventing data loss from access transistor degradation.

A segmented sense amplifier isolates data lines from bit lines using pass gate transistors and a current cut-off device.

Segmenting memory into isolated portions allows interleaved access requests that sustain full data bus utilization without increasing data granularity.

Detection cells monitor adjacent row activations to trigger targeted memory refreshes before charge leakage corrupts stored data.

A redundancy circuit programs defective memory cell addresses into electric fuses to confirm repair status.

Segmented word line selection reduces refreshing voltage and chip area costs in semiconductor memory devices with open bit line architecture.

An asymmetric magnetic memory element reverses magnetization through current flow along angled arms, eliminating the need for external magnetic fields.

An asynchronous memory interface repurposes double data rate pins to transmit device feedback signals.

Discharge elements connect PRAM bit lines to ground voltage before operations, preventing leakage current paths between word and bit lines.

A reference current generator uses parallel circuit sets with distinct resistance values to produce stable output signals.

Capacitive coupling between word line and power supply lines boosts cell voltage, improving static noise margin without timing penalties.