Memory Cell Access Circuit with Local Bitline Segmentation
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Solution Overview
Problem
Conventional DRAMs face challenges in achieving high transfer ratio and reducing bitline capacitance while maintaining reliable sense signal detection, particularly due to increased bitline capacitance with multiple memory cells connected to a single bitline, which limits the amplitude of the sense signal and complicates early masked write operations.
Innovation Solution
A circuit design featuring a local bitline connected to a local sense amplifier, with separate global bitlines and a secondary sense amplifier, utilizing a three-transistor local sense amplifier configuration that reduces bitline capacitance and allows for early masked writes without sharing charging current, thereby enhancing transfer ratio and reducing data pattern-dependent voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple memory cells are connected to a single bitline to achieve maximum density, then area overhead is reduced, but bitline capacitance increases and transfer ratio decreases
Solution Approach 1:
The bitline is segmented into local bitlines and global bitlines. Local bitlines connect to memory cells with low capacitance, while global bitlines handle signal distribution. This segmentation allows multiple cells per bitline (high density) while maintaining low local capacitance for high transfer ratio.
2Area of stationary object
If multiple memory cells are connected to a single bitline to achieve maximum density, then area overhead is reduced, but sense signal amplitude decreases
Solution Approach 1:
The sensing function is segmented between local sense amplifiers (connected to local bitlines with low capacitance) and global sense amplifiers. This allows high transfer ratio at the local level while maintaining high density through multiple cells per global bitline.
Solution Approach 2:
Local bitlines act as intermediaries between memory cells and global bitlines. They provide low-capacitance charge sharing for high transfer ratio, while global bitlines handle signal distribution, enabling both high density and high sense signal amplitude.
3Device complexity
If global bitline charging current is distributed through a path shared with neighboring cells, then device complexity is reduced, but data pattern dependent voltage drops increase
Solution Approach 1:
The charging current path is segmented into dedicated global bitline paths separate from cell access paths. This eliminates data pattern dependent voltage drops by preventing current sharing with neighboring cells, while the segmented architecture manages complexity through modular local and global sections.
4Area of stationary object
If a smaller local sense amplifier is used to reduce footprint, then area is reduced, but ability to sense small signals may be compromised
Solution Approach 1:
The sensing function is segmented into two stages: local sense amplifiers with small footprint that detect signals from low-capacitance local bitlines, and global sense amplifiers that provide additional amplification. The segmentation allows compact local amplifiers to maintain high sensitivity while the two-stage architecture ensures sufficient overall gain.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit achieves a higher transfer ratio, lower bitline capacitance, and supports early masked writes, reducing data pattern-dependent voltage drops and providing a smaller footprint compared to conventional designs, while maintaining reliable sense signal detection.
Implementation Method 1
the sense signal from a memory cell is generated by charge sharing the charge stored in the memory cell with a precharged bitline
Implementation Method 2
One way to amplify small sense signals has been shown to be a cross-couple sense amplifier
Implementation Method 3
a secondary sense amplifier connected to the first and second global bitlines
Data Source
AI summary
A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines.