Static Source Line STRAM Cell for Density Scaling
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Solution Overview
Problem
Conventional Spin-Transfer Torque RAM (STRAM) designs face challenges with asymmetric write currents and integration difficulties, limiting scaling and array density due to the requirement of two metal tracks for source and bit lines, and high power consumption as the MTJ size shrinks.
Innovation Solution
A spin-transfer torque memory array with a single static source line that provides a constant voltage for both high and low resistance states, reducing cell dimensions and balancing driving currents, allowing for improved array density and scaling by using a common source line for multiple magnetic tunnel junction cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two metal tracks are used in each column direction (one for source line and one for bit line), then the STRAM cell can function properly with asymmetric write currents, but the minimum width of each column increases, limiting array density
Solution Approach 1:
The patent merges the source line and bit line into a single metal track by using a dual-polarity write voltage scheme. The same physical line serves as both source and bit line depending on the polarity of the applied voltage, thereby reducing the number of metal tracks from two to one per column direction while maintaining full write functionality.
Solution Approach 2:
The single metal track is designed to perform multiple functions: it acts as the source line during forward write operations and as the bit line during reverse write operations. This multi-functionality is achieved through bidirectional current flow enabled by positive and negative write voltages, allowing one physical structure to replace what traditionally required two separate structures.
2Area of stationary object
If the MTJ size is reduced to improve scaling, then array density increases, but the switching magnetic field amplitude increases and switching variation becomes severe, leading to high power consumption
Solution Approach 1:
The patent changes the voltage parameter from unipolar to bipolar (dual-polarity) to enable bidirectional current flow through the MTJ. This parameter change allows the use of smaller MTJ sizes because the spin-transfer torque mechanism can effectively switch magnetization in both directions, maintaining switching efficiency at reduced dimensions without requiring excessive current that would lead to high power consumption.
3Reliability
If the driving transistor size is determined by reverse current requirements, then the high resistance state can be written, but the forward current becomes excessively large, increasing power consumption
Solution Approach 1:
The patent intentionally introduces asymmetry in the voltage application scheme: during forward write operations, a moderate positive voltage is applied, while during reverse write operations, a larger negative voltage is applied. This asymmetric voltage scheme compensates for the natural current asymmetry in the circuit, balancing the power consumption of forward and reverse write operations by adjusting the voltage magnitudes to achieve equalized current profiles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces STRAM cell dimensions, improves array density, and balances driving currents, enabling more efficient scaling and reduced power consumption while maintaining data storage capabilities.
Implementation Method 1
Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction cell
Implementation Method 2
Data storage is realized by switching the resistance of MTJ between a high-resistance state and a low-resistance state. MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ
Data Source
AI summary
A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.


