Configurable Memory Channels for Flexible Data Width and Burst Control
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Solution Overview
Problem
Existing memory devices lack flexibility in configuring data widths, memory array access, and data burst lengths across multiple channels, leading to inefficient utilization and compatibility issues with different memory controllers.
Innovation Solution
A configurable memory device that allows for adjustable data widths, memory array access, and data burst lengths across multiple channels, enabling non-uniform allocation and operation of memory channels with varying signal widths and array access, and supporting different clock frequencies and data block sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory devices use fixed data widths and channel configurations, then device complexity is reduced, but adaptability and compatibility with different memory controllers deteriorate
Solution Approach 1:
The patent implements dynamic configurability where data widths, memory array access patterns, and data burst lengths can be adjusted at runtime. The memory device allows reconfiguration of channel parameters through control signals, enabling the same physical hardware to adapt to different memory controller requirements without physical changes or complex multi-version design.
Solution Approach 2:
The memory device is designed with universal interfaces that can operate in multiple configurations. By incorporating configurable data widths (e.g., supporting both 64-bit and 128-bit modes), flexible memory array access (different bank groupings), and adjustable burst lengths, a single memory device can serve multiple memory controller types and applications, eliminating the need for specialized devices for each use case.
2Adaptability or versatility
If memory devices support multiple channel configurations with varying data widths, then adaptability improves, but device complexity increases
Solution Approach 1:
The memory device divides its data interfaces into multiple configurable groups or channels, where each channel can be independently configured with different data widths. The control circuitry segments the memory arrays into bank groups that can be dynamically assigned to different channels, allowing non-uniform allocation where some channels have wider data paths than others based on specific performance requirements.
Solution Approach 2:
The patent employs parameter change mechanisms where control signals modify operational parameters such as data width, burst length, and bank grouping without changing the physical hardware configuration. This allows the memory device to switch between different operational modes (e.g., from 64-bit to 128-bit data width) by changing control parameters, managing complexity through software/firmware control rather than hardware multiplication.
3Productivity
If fixed memory array access patterns are used, then device complexity is minimized, but productivity and data transfer efficiency deteriorate
Solution Approach 1:
The memory device implements dynamic memory array access patterns where bank groupings and channel assignments can be reconfigured based on workload requirements. The control circuitry can dynamically adjust which memory banks are accessed through which channels and in what patterns, optimizing data transfer efficiency for different access scenarios (sequential, random, interleaved) without requiring multiple fixed-configuration devices.
Data Source
AI summary
A memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data widths (i.e., number of data signals) allocated to each channel are configurable such that a given group of data input/output (I/O) signals may be part of a first channel in one configuration, but be part of another channel in a different configuration. Similarly, the memory arrays (e.g., banks, or bank groups) accessed by a given channel may be configurable such that a given memory array is accessed via a first channel in one configuration but is accessed via a different channel in a different configuration. Finally, the data burst length, data burst size, and data transfer clock cycle are configurable.