Inverter Circuit Mitigates Spurious Writes in Memory Devices

The patent introduces an intermediary inverter circuit between the driver circuitry and the transistors that control bitcell access. This inverter circuit acts as a mediator that conditions the control signals, ensuring that transistors remain properly blocked during negative voltage spikes on bitlines. The inverter circuit receives the control signal and generates an inverted control signal that maintains transistor gate voltages at appropriate levels, preventing spurious writes while allowing legitimate write operations to proceed at high speed.

The inverter circuit provides beforehand cushioning by preparing and conditioning control signals before they reach the transistors. By inverting and conditioning the control signals in advance, the circuit ensures that transistors are properly protected against negative voltage spikes before the spikes can cause erroneous writes. This preventive measure maintains transistor blocking capability throughout the write operation, including during mask write operations where some bitcells should not be updated.

The inverter circuit serves as an intermediary that processes control signals for all bitcells in a mask write operation uniformly. It ensures that transistors controlling unselected bitcells remain properly blocked even when negative voltage spikes occur on their associated bitlines. The inverter circuit receives the mask write control signal and generates inverted signals that maintain appropriate voltage levels on transistor gates, preventing spurious writes to unselected bitcells while allowing selected bitcells to be updated in parallel.

The patent applies local quality by providing individual inverter circuits for different transistor groups that control different bitcell sets. Each inverter circuit locally conditions control signals for its associated transistors, ensuring that each group of transistors is independently protected against spurious writes. This localized approach allows mask write operations to efficiently update multiple bitcells while maintaining precise control over which bitcells are actually written to, based on the mask pattern.