MRAM Synapse Memory Cell Layout for Read Disturb Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing synapse memories face issues with read disturb due to the influence of unselected synapse memory cells during read operations, particularly in large arrays, which can affect the accuracy and reliability of weight value retrieval.
Innovation Solution
The implementation of a synapse memory system with a cross-bar array configuration using magnetoresistive random access memory (MRAM) devices, equipped with three transistors (read, write, and common transistors) and controlled by specific voltage signals to manage read and write operations, minimizing the impact of unselected cells through transistor switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the array size of synapse memory is increased, then the storage capacity is improved, but the read disturb from unselected cells increases
Solution Approach 1:
The synapse memory array is segmented into multiple banks, with each bank independently controllable through row and column address decoding. This segmentation allows selective access to specific sub-arrays, isolating unselected cells and reducing read disturb effects while maintaining large overall storage capacity through the combined banks.
2Quantity of substance
If the array size of synapse memory is increased, then the storage capacity is improved, but the accuracy of weight value retrieval deteriorates
Solution Approach 1:
Sense amplifiers are introduced as intermediary components between the memory cells and readout circuits. These sense amplifiers detect and amplify the small voltage signals from selected memory cells while rejecting interference from unselected cells, thereby maintaining high measurement precision for weight value retrieval even in large arrays.
3Ease of operation
If three transistors are added to each memory cell, then the control over read and write operations is improved, but the device complexity increases
Solution Approach 1:
The three transistors in each memory cell are designed with multi-functional capabilities. The read transistor, write transistor, and common transistor collectively perform both read and write operations through different voltage signal combinations, eliminating the need for separate dedicated circuits and reducing overall system complexity despite the increased cell-level transistor count.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces read disturb, allows for larger array sizes, and ensures independent and accurate read and write operations without undesired inputs or outputs, enhancing the performance and reliability of synapse memory systems.
Implementation Method 1
Each of the synapse memory cells may include a magnetoresistive random access memory (MRAM) device
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A synapse memory includes a memory device configured to store a weight value. The memory device includes a read terminal, a write terminal, and a common terminal, the read terminal being configured to receive a read signal, the write terminal being configured to receive a write signal, and the common terminal being configured to output an output signal from the memory device. The synapse memory also includes a write transistor provided between the write terminal of the memory device and a write signal line configured to send the write signal. The synapse memory further includes a common transistor provided between the common terminal of the memory device and one of the dendrite lines.