3D DRAM Cylindrical Capacitor Stack for Higher Integration Density
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration density and large capacitor capacity due to structural limitations, particularly in three-dimensional dynamic random access memories (3D DRAMs) with multilayer horizontal cells.
Innovation Solution
A semiconductor device with a stack structure featuring cylindrical first electrodes supported by a support structure, surrounded by a dielectric layer and a second electrode layer, allowing for longer electrodes and improved integration through a manufacturing method involving deposition and etching processes without additional patterning steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor structures are used, then manufacturing processes are simpler, but integration density and capacitor capacity are limited
Solution Approach 1:
The patent transitions from planar 2D structures to three-dimensional stacked structures, arranging memory cells and capacitors in vertical layers. This dimensional change enables significantly higher integration density by utilizing the third dimension (height) for stacking multiple functional layers, including word lines, bit lines, and capacitor structures, thereby increasing the quantity of functional elements per chip area without proportionally increasing manufacturing complexity
Solution Approach 2:
The patent implements nested structures where cylindrical electrodes are surrounded by dielectric layers, which are in turn surrounded by conductive layers forming capacitors. These nested cylindrical structures are then stacked vertically within the three-dimensional architecture, creating compact nested arrangements that maximize space utilization and increase integration density while maintaining manufacturability through standardized deposition and etching processes
2Quantity of substance
If electrode length is increased to boost capacitor capacity, then chip space usage improves, but structural stability and manufacturing difficulty worsen
Solution Approach 1:
Instead of extending electrodes horizontally in a single plane, the patent stacks multiple electrode structures vertically in three dimensions. This allows the effective electrode length (and thus capacitor capacity) to increase through vertical stacking of multiple layers, while each individual electrode maintains manageable dimensions and structural stability. The vertical stacking approach enables longer effective electrode paths without compromising the stability of individual electrode structures
Solution Approach 2:
The patent divides the capacitor structure into multiple discrete cylindrical electrode segments stacked vertically, with each segment having controlled length and dimensions. This segmentation allows each electrode segment to maintain structural stability while the cumulative effect of multiple segments provides the increased electrode length needed for higher capacitor capacity. Each segmented electrode can be manufactured with consistent quality, ensuring reliability
3Manufacturing precision
If additional patterning steps are added to achieve complex structures, then manufacturing precision improves, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent employs universal deposition and etching processes that can create multiple structural features simultaneously. For example, atomic layer deposition (ALD) is used to form both dielectric layers and conductive layers with precise thickness control, and etching processes create both cylindrical electrode shapes and patterned openings. This multi-functionality of manufacturing processes achieves high manufacturing precision for complex three-dimensional structures without requiring additional specialized patterning steps, thereby controlling manufacturing costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables larger capacitor capacity and efficient use of chip space, enhancing integration level and product yield while reducing manufacturing costs.
Implementation Method 1
a first dielectric layer C3 and a second electrode layer C4, wherein the first dielectric layer C3 covers at least a part of an inner surface of the first electrode, at least a part of an outer surface between the first end and the second end, and at least a part of a surface of the support structure
Implementation Method 2
A semiconductor device with a stack structure featuring cylindrical first electrodes supported by a support structure, surrounded by a dielectric layer and a second electrode layer, allowing for longer electrodes and improved integration through a manufacturing method involving deposition and etching processes
Data Source
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AI summary
Provided are a semiconductor device, a method for manufacturing the same, and a three-dimensional dynamic random access memory. The semiconductor device includes a substrate and a stack structure disposed on the substrate. The stack structure includes a support structure and memory cells stacked along a first direction. Each of the memory cells includes a cylindrical first electrode extending along a second direction; the first electrode includes a first end and a second end along the second direction, the first end is blind, and the second end has an opening and is connected to the support structure. The support structure includes a first part surrounding a part of an outer surface of the first electrode.