DRAM Phase Adjustment Circuit for LPDDR Signal Synchronization
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Solution Overview
Problem
LPDDR DRAMs experience data access errors due to varying phase differences between clock and control/address signals, which change with temperature, voltage, and manufacturing processes, requiring a system to maintain a constant phase difference.
Innovation Solution
A DRAM controller with a phase adjustment circuit that delays the clock signal, samples control and address signals at different times, compares the samples to generate a status signal, and adjusts the phase difference to maintain synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of the control and address bus is doubled to achieve higher data rate, then the data transmission speed is improved, but the phase difference between clock signal and control/address signals becomes more sensitive to temperature and voltage variations
Solution Approach 1:
The patent implements a phase detection mechanism that continuously monitors the phase difference between the clock signal and control/address signals. When phase deviation is detected, the system generates feedback signals to adjust the timing of control and address signals, thereby maintaining synchronization despite temperature and voltage variations. This feedback loop ensures reliable operation at doubled data rates.
Solution Approach 2:
The patent introduces dynamic phase adjustment capabilities that allow the timing of control and address signals to be adjusted in real-time based on operating conditions. By making the phase relationship dynamic rather than fixed, the system can adapt to temperature and voltage changes while maintaining accurate sampling at the higher doubled frequency.
2Reliability
If automatic phase adjustment is implemented to maintain constant phase difference, then the data access reliability is improved, but the device complexity increases
Solution Approach 1:
The patent implements a self-adjusting phase alignment mechanism where the DRAM controller automatically detects and corrects phase deviations without external intervention. The system uses built-in phase detection circuits that monitor signal timing and autonomously adjust control and address signal phases, eliminating the need for complex external calibration equipment or manual adjustment mechanisms.
Solution Approach 2:
The patent integrates the phase detection and adjustment functionality directly into the existing DRAM controller architecture, merging multiple functions into a unified control unit. By combining phase monitoring, detection, and adjustment operations within the same control logic, the system achieves reliable phase synchronization without adding separate complex subsystems.
Data Source
AI summary
The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal.