Selection Element Doping Layout for Uniform Memory Cell Thresholds
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving uniform threshold voltages and characteristics among memory cells due to variations in their positions, leading to inconsistent operation.
Innovation Solution
The semiconductor device is designed with a cell area divided into sub-cell areas, where memory cells closer to peripheral circuit areas have higher dopant concentrations in their selection element layers, ensuring uniform threshold voltages and stable operation across all memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are disposed at different positions in the cell area, then the device can accommodate more memory cells, but the threshold voltage becomes non-uniform across different positions
Solution Approach 1:
The patent applies local quality by dividing the cell area into multiple sub-cell areas and assigning different dopant concentrations to selection element layers in different sub-cell areas. Specifically, sub-cell areas closer to peripheral circuit areas receive higher dopant concentrations, while those farther away receive lower dopant concentrations. This spatial variation in material composition compensates for position-dependent threshold voltage variations, achieving uniform threshold voltages across all memory cells regardless of their positions.
Solution Approach 2:
The patent changes the dopant concentration parameter of the selection element layers based on position within the cell area. By adjusting this physical parameter (dopant concentration) across different sub-cell areas, the invention compensates for positional variations and achieves uniform threshold voltage characteristics throughout the entire cell area, enabling consistent operation of all memory cells.
2Area of stationary object
If memory cells are disposed at different positions in the cell area, then the device area is fully utilized, but the operation characteristics become inconsistent
Solution Approach 1:
The patent implements local quality by creating position-dependent dopant concentration profiles in the selection element layers. Different sub-cell areas receive tailored dopant concentrations that locally compensate for their specific positional characteristics relative to peripheral circuit areas. This ensures that all memory cells, regardless of their location within the cell area, exhibit consistent operation characteristics and reliability.
Solution Approach 2:
The patent modifies the dopant concentration parameter as a function of position within the cell area. By systematically varying this parameter across different sub-cell areas, the invention achieves uniform operation characteristics throughout the entire cell area, ensuring reliable and consistent performance of all memory cells while maximizing area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves uniform threshold voltages and stable operation of memory cells, regardless of their positions, by adjusting dopant concentrations in selection element layers, thereby stabilizing the characteristics and operations of all memory cells.
Implementation Method 1
A dopant concentration of the first selection element layer is lower than a dopant concentration of the second selection element layer
Data Source
AI summary
A semiconductor device includes a cell area including a first sub-cell area and a second sub-cell are; a first peripheral circuit area adjacent to one side of the cell area in a first direction; and a second peripheral circuit area adjacent to another side of the cell area in a second direction perpendicular to the first direction. The first sub-cell area includes a first memory cell disposed closer to the first and second peripheral circuit areas than the second memory cell. The second sub-cell area includes a second memory cell disposed farther from the first and second peripheral circuit areas. The first and second memory cells include first and second selection element layers, respectively, each selection element layer including a dielectric material containing a dopant. A dopant concentration of the first selection element layer is lower than a dopant concentration of the second selection element layer.