3D Ferroelectric Memory String Arrays for High Density
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Solution Overview
Problem
Existing ferroelectric field-effect transistors (FeFETs) in memory circuits suffer from low endurance, making them unsuitable for many memory applications, and conventional memory systems have low retention time and density.
Innovation Solution
The formation of FeFETs in stacks of horizontal active strips with vertical control gate electrodes and ferroelectric elements, organized as NOR memory strings, allowing for high-density memory arrays with reduced read-latency, power dissipation, and concurrent operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory structures are used, then manufacturing simplicity is maintained, but memory density and retention time remain low
Solution Approach 1:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertically stacked structures. Multiple active strips are stacked in the vertical direction with control gates positioned between strips, enabling significantly higher memory density by utilizing the third dimension (Z-axis) for stacking multiple memory cells per horizontal plane.
Solution Approach 2:
The patent implements a nested configuration where control gates are positioned between and around active strips in a stacked arrangement. The control gates are embedded within the stack structure, with each control gate controlling multiple floating gate electrodes that are nested between the active strips, creating a compact multi-layered nested structure.
2Loss of time
If conventional memory structures are used, then device simplicity is maintained, but read-latency and power dissipation are high
Solution Approach 1:
The vertical stacking configuration reduces read-latency by shortening the electrical path length between control gates and memory cells. The three-dimensional arrangement allows for more direct signal routing and reduced parasitic effects compared to planar structures, improving access speed despite increased structural complexity.
Solution Approach 2:
The memory array is segmented into multiple independently controllable active strips stacked vertically. Each active strip can be selectively accessed through its associated control gate, enabling parallel operation and reducing overall access time by dividing the memory space into separable, independently addressable units.
3Duration of action of stationary object
If ferroelectric elements are added to improve retention, then disturbance conditions increase requiring refresh operations
Solution Approach 1:
The patent implements refresh operations that monitor and restore the state of ferroelectric memory cells. The control circuitry detects disturbance conditions in the ferroelectric elements and performs corrective refresh operations to maintain data integrity, creating a feedback loop that manages the trade-off between enhanced retention and increased disturbance susceptibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high memory density, reduced read-latency, and lower cost-per-bit, while mitigating disturb conditions through refresh operations, resulting in stable and reliable memory performance.
Implementation Method 1
Polarization of the polarizable element in an FeFET changes the threshold voltage the FeFET
Implementation Method 2
one or more polarizable or ferroelectric elements (also referred to as 'ferroelectric or polarization layers')
Data Source
AI summary
Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.