Ferroelectric Memory Cell Structure for 3D Multi-State Storage
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of fine pattern forming technology, while three-dimensional semiconductor memory devices face challenges in achieving high integration and efficient data storage states.
Innovation Solution
A semiconductor memory device with a substrate, alternating gate electrodes and interlayer dielectric layers, incorporating ferroelectric and charge trap patterns, and vertical channel structures to enhance data storage capabilities and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited by expensive fine pattern forming technology
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked vertically with gate electrodes extending in the vertical direction, enabling higher integration without requiring extreme fine pattern forming technology. This dimensional change allows the device to overcome the practical limitations of two-dimensional scaling while maintaining manufacturability.
2Manufacturing precision
If three-dimensional semiconductor memory devices are implemented, then integration is improved, but achieving high integration and efficient data storage states becomes challenging
Solution Approach 1:
The patent employs a composite gate insulating layer structure consisting of a first gate insulating layer and a second gate insulating layer with different dielectric materials. The first layer provides baseline insulation while the second layer with higher dielectric constant enables stronger electric field control. This composite structure allows efficient control of charge trap states and enables multi-threshold voltage operation, improving data storage efficiency in the three-dimensional architecture.
Solution Approach 2:
The patent introduces charge trap regions with specific conductivity types at localized positions within the channel region. By controlling the conductivity type and distribution of charge traps locally, the patent enables different threshold voltage states in different regions, facilitating multi-state memory operation and improving data storage efficiency without increasing overall device complexity.
3Device complexity
If conventional gate insulating layers are used, then device structure is simpler, but memory window and erase operation speed are limited
Solution Approach 1:
The patent uses a composite gate insulating layer structure where the second gate insulating layer has higher dielectric constant than the first layer. This composite structure enhances the electric field effect on charge trap regions, enabling faster charge trapping and release during write and erase operations. The higher dielectric constant material allows stronger coupling between gate electrode and channel, improving erase operation speed while maintaining reasonable device complexity.
Solution Approach 2:
The patent changes the dielectric constant parameter of the gate insulating layer by introducing a second layer with higher dielectric constant material. This parameter change enhances the electric field strength for a given gate voltage, enabling faster charge transfer to and from trap regions. The modified dielectric parameter directly improves erase operation speed and enlarges the memory window without requiring fundamentally more complex device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enables a larger memory window and faster erase operations, allowing for multi-state memory devices with improved integration and reduced operation time.
Implementation Method 1
the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling
Implementation Method 2
band-to-band tunneling in gated p-i-n junction
Data Source
Figure 1
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Figure 2B
AI summary
A semiconductor memory device may include a substrate (10), first (20) and second (30) impurity regions on the substrate, first (40) and second (50) gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode (60) on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.