RRAM Write Verify Using Resistance Trend Detection
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Solution Overview
Problem
Existing RRAM devices lack the ability to determine the changing trend of resistance values during write or reverse write operations, leading to inefficient power consumption and reduced reliability due to continued application of pulses in non-expected trends.
Innovation Solution
A RRAM device with a comparator and local counter system that compares sensed resistance values to reference values to determine the trend, allowing for informed decision-making on whether to continue set or reset operations, thereby optimizing power usage and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write or reverse write pulses are continuously applied to RRAM cell, then the operation completes eventually, but power consumption increases and time is wasted when resistance value changes in non-expected trend
Solution Approach 1:
The patent implements a feedback mechanism by comparing the resistance value before and after applying write pulses. The comparator generates a verification signal based on the resistance change trend, which feeds back to the memory controller to determine whether to continue applying pulses. This feedback loop enables the system to detect when the resistance value is changing in a non-expected trend and stop pulse application, thereby reducing power consumption while maintaining write operation reliability.
Solution Approach 2:
Instead of continuously applying write pulses until a fixed time limit or predetermined number of pulses, the patent applies pulses only as long as the resistance value shows expected changing trend. This partial action approach stops pulse application early when the trend becomes non-expected, avoiding excessive power consumption while still achieving reliable write operations when the resistance reaches the target value.
2Reliability
If write or reverse write pulses are continuously applied to RRAM cell, then the operation persists, but time consumption increases when resistance value does not reach target value
Solution Approach 1:
The feedback mechanism monitors the resistance change trend after each write pulse and provides real-time information to the memory controller. When the resistance value fails to change in the expected direction, the verification signal indicates this to the controller, which immediately terminates further pulse application. This feedback-driven early termination significantly reduces time consumption compared to continuous pulse application, while maintaining reliability by stopping only when the trend indicates failure.
Solution Approach 2:
The patent enables the write operation to skip unnecessary subsequent pulses by detecting non-expected resistance trend early. Instead of persisting through all predetermined pulses or time periods, the system rushes through the verification process and terminates the operation as soon as failure is detected, thereby reducing time loss while preserving reliability for successful write operations.
3Device complexity
If resistance value trend is not monitored, then the write operation is simple, but power consumption increases due to unnecessary pulse application
Solution Approach 1:
The patent introduces a feedback-based verification mechanism that compares resistance values before and after write pulses. The comparator and verification signal generation add minimal complexity to the write operation, yet this simple feedback loop effectively detects non-expected resistance trends and prevents unnecessary pulse application, achieving significant power consumption reduction with only moderate increase in operational complexity.
Solution Approach 2:
The patent replaces complex continuous monitoring and control mechanisms with a simpler electronic verification system using comparators and digital logic. Instead of continuously measuring and analyzing resistance trends with complex algorithms, the system uses straightforward voltage comparison and binary verification signals to detect trend changes, reducing overall system complexity while effectively managing power consumption.
Data Source
AI summary
This invention introduces a resistive random access memory (RRAM) device, a write verify method and a reverse write verify thereof which are capable of improving the performance of RRAM operations and improving the uniform performance for each RRAM cell. A first resistance value sensed from a RRAM cell is compared with a plurality of reference resistance values to obtain a comparison value. A set or a reset operation is performed on the RRAM cell by applying a first set or reset pulse to change the first resistance value to a second resistance value. Next, the second resistance value is compared with the comparison value to determine whether to continue the set or reset operation on the RRAM cell.