Dynamic Refresh Rate Adjustment in Memory Self-Refresh

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Solution Overview

Problem

Memory systems face challenges in managing power consumption while maintaining data reliability during self-refresh states, as higher refresh rates consume more power but may lead to decreased reliability if the refresh rate is too low.

Innovation Solution

The memory system enters a self-refresh state and initially executes refresh operations at a fast refresh rate. Once all rows of memory cells are refreshed, the system decreases the refresh rate to a slower rate, using circuitry with a counter to ensure each row is refreshed at least once before reducing the rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the refresh rate is increased to maintain data reliability during self-refresh states, then data reliability is improved, but power consumption increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by transitioning the refresh rate from a static fixed value to a dynamic adjustable parameter. The system initially operates at a first refresh rate to ensure data reliability, then transitions to a second refresh rate after verifying data integrity, allowing the refresh rate to adapt to different operational phases and balance reliability with power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the refresh rate parameter from a constant to a variable that can take different values (first refresh rate and second refresh rate). By modifying this parameter based on operational conditions and data integrity verification results, the system optimizes the trade-off between maintaining data reliability and reducing power consumption during self-refresh states.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If the refresh rate is decreased to reduce power consumption during self-refresh states, then power consumption is reduced, but data reliability decreases

Engineering Contradiction:
Improvepower consumptionVSAvoiddata reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by performing data integrity verification before transitioning to the lower second refresh rate. The system first ensures data reliability at the initial first refresh rate, verifies integrity through read operations, and only then reduces the refresh rate, preventing reliability issues before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback through data integrity verification mechanisms that monitor whether data remains reliable after refresh operations. Based on this feedback from verification results, the system dynamically adjusts the refresh rate, increasing or maintaining it when reliability is compromised and reducing it when reliability is confirmed, creating a closed-loop control system.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250069638A1Adjusting refresh rate during self-refresh state
Publication Date: 2025.02.27 MICRON TECHNOLOGY INC
  • US20250069638A1 patent drawing
  • US20250069638A1 patent drawing
  • US20250069638A1 patent drawing

AI summary

Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.