I/O Line Precharge Circuit Auxiliary Current Control

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Solution Overview

Problem

In semiconductor memory devices, the precharge operation for input/output lines leads to significant core voltage VCORE current consumption, especially in higher data modes like x16, causing voltage level reductions and potential errors during write and read operations due to the inability of the core voltage driver to follow the operation demands.

Innovation Solution

An auxiliary current is supplied during the precharge operation interval to maintain the core voltage VCORE level, controlled by a precharge controller that adjusts the source voltage VDD based on the data input/output mode, ensuring stable voltage levels and reducing current consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the precharge operation uses only the main current from core voltage VCORE, then the precharge function is simple to implement, but the core voltage VCORE level reduces significantly causing potential errors

Engineering Contradiction:

Improvevoltage level stabilityVSAvoidprecharge circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the main current from core voltage VCORE with an auxiliary current from source voltage VDD during precharge operations. The precharge portion includes first precharge transistors connected to VCORE and second precharge transistors connected to VDD, merging both current sources to supply precharge current to the main input/output lines, thereby preventing VCORE level reduction without excessive complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a precharge controller as an intermediary component that manages the auxiliary current supply from VDD. The controller receives control signals and selectively activates the second precharge transistors to supplement the main current, acting as a mediator between the VDD power source and the precharge operation to maintain voltage stability

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the core voltage driver supplies high current continuously, then the voltage level is maintained during precharge, but the current consumption increases significantly

Engineering Contradiction:

Improvevoltage level stabilityVSAvoidcurrent consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic action by enabling the auxiliary current from VDD only during the precharge operation interval. The precharge controller activates the second precharge transistors temporarily when precharge is needed, then deactivates them afterward, allowing the main current to handle normal operations alone, thus reducing overall current consumption while maintaining voltage stability during critical precharge periods

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent applies local quality by providing different current sources for different operational conditions. The main current from VCORE handles normal operations, while the auxiliary current from VDD is specifically applied during precharge operations when high current is needed, optimizing energy usage by matching current supply to operational requirements

Inventive Principle:

Principle #3Local quality

3Productivity

If the precharge operation is performed with high current demand, then the precharge speed is fast, but the core voltage VCORE cannot follow the operation demands causing voltage level reduction

Engineering Contradiction:

Improveprecharge speedVSAvoidvoltage level stability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent merges the main current from VCORE with the auxiliary current from VDD to provide high total current during precharge operations. This combined current supply enables fast precharge speed by meeting the high current demand, while the auxiliary current from VDD prevents VCORE level reduction by supplementing the main current source

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7525857B2Input/output line precharge circuit and semiconductor memory device including input/output line precharge circuit

Publication Date: 2009.04.28 SK HYNIX INC

AI summary

An input/output line precharge circuit to further supply an auxiliary current other than a main current for precharge for a predetermined time on a precharge operation interval, and includes a write driver that transmits data received or transmitted via a global input/output line to a main input/output line, a precharge portion that precharges the main input/output line with a main current, and a precharge controller that supplies an auxiliary current for precharge for a predetermined time on a precharge operation interval to the precharge portion, and the precharge controller includes a voltage supply controller for generating a pulse to control a supply of the auxiliary current in response to at least one of the write enable signal, precharge signal, or data input/output mode signal; and a voltage supply portion supplying the auxiliary current to the precharge portion by a pulse outputted from the voltage supply controller.