Ferroelectric Memory Cell Structure to Reduce Disturb
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Solution Overview
Problem
Existing ferroelectric memory devices face issues with disturb during operation, which affects the reliability and performance of the memory storage.
Innovation Solution
The introduction of a series connected select gate transistor reduces disturb by incorporating a first field effect transistor with a non-ferroelectric gate dielectric and a second field effect transistor with a ferroelectric gate dielectric, forming a unique structure with semiconductor channels and gate electrodes that minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ferroelectric memory device structure is used, then the device can store information using ferroelectric material, but disturb occurs during operation which reduces reliability
Solution Approach 1:
The memory device is divided into two separate transistors: a first transistor with non-ferroelectric gate dielectric and a second transistor with ferroelectric gate dielectric. This segmentation allows the ferroelectric material to be isolated in one transistor, reducing its harmful disturbance effect on other cells while maintaining its useful memory storage function in the second transistor.
Solution Approach 2:
The first transistor with non-ferroelectric gate dielectric acts as an intermediary element between the control circuitry and the ferroelectric memory transistor. This intermediary structure mediates the control signals and reduces the direct disturbance from the ferroelectric material, allowing reliable operation while preserving memory functionality.
2Reliability
If ferroelectric material is used for memory storage, then data can be retained, but disturb during operation affects performance
Solution Approach 1:
By separating the ferroelectric material into a dedicated second transistor, the device maintains data retention capability while isolating the disturbance effect. The first transistor handles control functions without ferroelectric disturbance, while the second transistor preserves memory storage with minimized interference on surrounding cells.
Solution Approach 2:
The ferroelectric material is localized specifically in the second transistor's gate dielectric, allowing data retention in that region while the first transistor and surrounding areas experience reduced disturbance. This local concentration of ferroelectric property achieves both data retention and reduced harmful effects.
3Object-affected harmful factors
If a series connected select gate transistor structure is implemented, then disturb is reduced, but device complexity increases
Solution Approach 1:
The memory cell is segmented into two transistors connected in series, where each transistor has a specific function. This segmentation reduces disturb by isolating the ferroelectric material to one transistor, and the increased complexity is justified by the significant improvement in reliability and disturbance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the operational stability and reliability of ferroelectric memory devices by reducing disturb, thereby improving data retention and overall performance.
Implementation Method 1
A ferroelectric material refers to a material that displays spontaneous polarization of electrical charges in the absence of an applied electric field. The net polarization P of electrical charges within the ferroelectric material is non-zero in the minimum energy state.
Implementation Method 2
Polarization P of a ferroelectric material as a function of an applied voltage V thereacross displays hysteresis.
Implementation Method 3
The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring electrical current passing through a semiconductor channel provided adjacent to the ferroelectric material in a field effect transistor ferroelectric memory device.
Data Source
Figure 1A
Figure 1B
Figure 1C~1D
AI summary
A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.