Semiconductor Memory Cell Testing with Inverted Data Buffers
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Solution Overview
Problem
Conventional methods for testing memory cells in semiconductor devices are time-consuming due to the need to individually write, read, and compare data across numerous cells, and fail to accurately detect defective cells when signal lines are shorted, leading to inefficiencies and misdiagnosis.
Innovation Solution
A semiconductor device with a control unit that generates control signals to selectively apply either original or changed data to memory cells through buffers, allowing for simultaneous testing and accurate detection of defective cells even with shorted signal lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If individual memory cells are tested by writing, reading and comparing data sequentially, then testing accuracy is maintained, but testing time increases significantly
Solution Approach 1:
The patent combines multiple individual memory cell tests into a single simultaneous test operation. By applying the same test data to multiple memory cells through different buffers and then reading back all results simultaneously, the system achieves parallel testing that dramatically reduces total testing time while maintaining accuracy through subsequent individual comparison of each cell's output against the original test data
Solution Approach 2:
The patent segments the testing process into distinct phases: a write phase where test data is simultaneously applied to multiple memory cells through different buffers, and a read phase where results are simultaneously read back. This segmentation allows parallel operation during critical paths while maintaining individual cell test integrity through separate read operations for each cell
2Productivity
If multiple memory cells are tested simultaneously by writing, reading and comparing similar test data, then testing efficiency increases, but the ability to detect defective cells with shorted signal lines deteriorates
Solution Approach 1:
The patent applies local quality by using different buffer configurations for different memory cells being tested simultaneously. Each buffer can be independently controlled to apply either original data or inverted data to its associated memory cell, allowing localized differentiation of test patterns even during parallel testing. This enables detection of shorted signal lines by comparing expected vs. actual outputs for each individual cell
Solution Approach 2:
The patent uses data inversion as a diagnostic technique to detect shorted signal lines. By inverting the test data for certain memory cells through buffer control and then comparing the inverted results against expected inverted values, the system can identify defective cells that would otherwise be indistinguishable during simultaneous testing. If a cell with a shorted line produces incorrect inverted output, the defect is revealed
3Measurement precision
If control signals are used to selectively apply original or changed data to memory cells, then defective cell detection accuracy improves, but device complexity increases
Solution Approach 1:
The patent implements a universal buffer design that can perform multiple functions: normal data transmission, data inversion, and test mode control. The same buffer circuitry is used for both operational memory functions and diagnostic testing, with control signals switching between modes. This multi-functionality reduces the need for separate dedicated test equipment and minimizes overall device complexity while maintaining high detection accuracy
Data Source
AI summary
Disclosed are a semiconductor device capable of testing memory cells and a test method. The semiconductor device includes a plurality of terminals, each terminal being configured to receive similar data during a test mode, a plurality of buffers, each buffer being configured to receive data from a corresponding terminal and output either the data or changed data to a corresponding memory cells in response to a control signal, and a control unit configured to generate a plurality of control signals, each control signal being respectively applied to a corresponding buffer.