Segmented DRAM Data Lines for Higher Bandwidth Density
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Solution Overview
Problem
As technology nodes shrink, DRAM devices face challenges in maintaining high memory cell density while increasing memory bandwidth without introducing physical gaps and dummy columns, which waste chip area and increase costs.
Innovation Solution
The memory device employs a segmented data line structure where data lines are divided into line segments, allowing for increased bandwidth without physical gaps or dummy columns, and uses line segment multiplexing outside the sense amplifier region to maintain high cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data lines are segmented into multiple line segments to increase memory bandwidth, then memory bandwidth is improved, but device complexity increases
Solution Approach 1:
The data lines are divided into multiple line segments along the extension direction. Each data line includes a first line segment and a second line segment adjacent to each other, allowing parallel data transmission through multiple segments while maintaining organized structure through systematic coupling arrangements.
Solution Approach 2:
The patent introduces a segmentation dimension to the data line structure by dividing continuous data lines into discrete line segments. This dimensional transformation enables increased bandwidth through parallel transmission paths while the segments remain organized along the extension direction, managing complexity through structured arrangement.
2Quantity of substance
If data lines are segmented without physical gaps or dummy columns, then memory cell density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Data lines are segmented into multiple line segments that are disposed along the extension direction with adjacent segments forming continuous conductive paths. This segmentation enables increased bandwidth while maintaining continuous electrical connection, eliminating the need for dummy columns and physical gaps that would reduce cell density.
Solution Approach 2:
The line segments serve multiple functions: they enable parallel data transmission for increased bandwidth while simultaneously forming continuous conductive paths without gaps. This multi-functionality allows the structure to achieve both high density and continuous connectivity without requiring separate dummy columns or gap structures.
3Quantity of substance
If line segment multiplexing is implemented outside sense amplifier region, then memory cell density is improved, but device complexity increases
Solution Approach 1:
The line segment multiplexing functionality is extracted from the sense amplifier region and implemented through a separate column selection circuit. This extraction allows the sense amplifier region to remain dedicated to its primary function while the column selection circuit handles the multiplexing of line segments, thereby maintaining high cell density in the sense amplifier region.
Solution Approach 2:
The column selection circuit acts as an intermediary between the bitlines and the segmented data lines. It selectively couples bitlines to appropriate line segments, enabling complex multiplexing functionality outside the sense amplifier region while keeping the sense amplifier region simple and dense with memory cells.
Data Source
AI summary
A memory device includes sets of bitlines, a column selection circuit, and a set of data lines including a first data line and a second data line. The sets of bitlines includes a first set of bitlines and a second set of bitlines. Each data line includes line segments disposed along an extension direction. The column selection circuit couples between the sets of bitlines and the set of data lines. The column selection circuit selectively couples a first bitline in the first set of bitlines and a first bitline in the second set of bitlines to a first line segment and second line segment of the first data line, respectively, and to selectively couple a second bitline in the first set of bitlines and a second bitline in the second set of bitlines to a first line segment of the second data line.