Memory Segmentation for Full Data Bus Utilization
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Solution Overview
Problem
Current memory technologies face challenges in achieving full data bus utilization without increasing data granularity or requiring multiple memories, leading to inefficiencies and performance issues due to idle time on the data bus.
Innovation Solution
A memory system comprising two electrically isolated memory portions with an interface that allows independent manipulation, enabling interleaving of access requests to achieve full data bus utilization without increasing data granularity or implementing burst mode or multiple memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If burst mode is used to improve data bus utilization, then data bus utilization is improved, but data granularity is increased
Solution Approach 1:
The memory is divided into multiple independently accessible memory portions (first memory portion and second memory portion), each with its own sense amplifiers. This segmentation allows interleaved access patterns where different memory portions can be accessed simultaneously or in rapid succession, improving data bus utilization without requiring burst mode and thus avoiding increased data granularity.
Solution Approach 2:
Instead of improving data bus utilization through temporal multiplexing (burst mode), the patent introduces a spatial dimension by dividing the memory into multiple portions. This allows parallel or interleaved access across different memory portions, achieving full data bus utilization while maintaining base granularity through independent access to each portion.
2Productivity
If multiple memories are implemented to achieve full data bus utilization, then data bus utilization is improved, but device complexity is increased
Solution Approach 1:
Multiple memory portions share common control lines and the data bus, merging the functionality of multiple independent memories into a single integrated structure. This allows full data bus utilization through interleaved access to different portions while avoiding the complexity of managing multiple separate memory devices with independent control logic.
Solution Approach 2:
The memory portions are designed to be electrically isolated yet functionally unified, sharing common control infrastructure. This universal design allows any memory portion to be accessed at any time through the same control interface, achieving high data bus utilization without the complexity of multiple independent memory systems.
3Ease of operation
If electrical isolation is introduced between memory portions to enable independent manipulation, then ease of operation is improved, but device complexity is increased
Solution Approach 1:
The interface acts as an intermediary component that manages the electrical isolation between memory portions while providing a unified control interface. This intermediary structure enables independent manipulation of different memory portions through controlled signal routing, achieving ease of operation without requiring complex isolation mechanisms that would increase overall device complexity.
Data Source
AI summary
A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.