Semiconductor Memory Write Assist Circuit Using Auxiliary Lines
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Solution Overview
Problem
The power consumption of write assist circuits in semiconductor memory devices, particularly in SRAMs, increases with large capacitance, necessitating a reduction in power consumption and area without compromising performance.
Innovation Solution
The semiconductor memory device incorporates multiple word lines, bit line pairs, auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit, where auxiliary line pairs run parallel to bit line pairs, allowing the write assist circuits to drive parasitic capacitance and reduce power consumption by utilizing these capacitances for negative bias generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write assist circuit drives a large capacitance to maintain negative bias for miniaturized memory cells, then the write margin is secured, but the power consumption increases
Solution Approach 1:
The bit line structure is segmented into a true bit line and a complementary bit line, where the complementary bit line is driven to negative bias by the write assist circuit. This segmentation allows the negative bias to be applied selectively to one line, reducing the total capacitance that needs to be driven compared to biasing both lines, thereby reducing power consumption while maintaining write margin.
Solution Approach 2:
The write assist circuit applies negative bias excessively to the complementary bit line (going below ground potential) to ensure adequate write margin for miniaturized cells. This partial excessive action on one line compensates for the reduced drive strength, securing reliable writes without needing to over-drive both lines, thus managing power consumption effectively.
2Reliability
If the write assist circuit is designed to drive large capacitance, then negative bias is maintained for miniaturized memory cells, but the area of the SRAM increases
Solution Approach 1:
The write assist function is segmented to operate on only the complementary bit line rather than both bit lines. This reduces the capacitance load and allows the use of smaller drive transistors in the write assist circuit, thereby reducing the area occupied by the write assist circuit while maintaining adequate negative bias for reliable writes in miniaturized memory cells.
Solution Approach 2:
The negative bias generation is applied locally to only the complementary bit line where it is most needed for write assist, rather than uniformly across the entire bit line structure. This localized approach reduces the overall capacitance that must be driven, allowing for smaller write assist transistors and reduced SRAM area while maintaining write margin for miniaturized cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the power consumption and area of the write assist circuits, enhancing the write and read speeds while maintaining adequate write margins for miniaturized memory cells.
Implementation Method 1
auxiliary line pairs, allowing the write assist circuits to drive parasitic capacitance and reduce power consumption by utilizing these capacitances for negative bias generation
Data Source
AI summary
Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.