Redundancy Circuit Fuse Address Programming

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Solution Overview

Problem

The existing redundancy circuits in semiconductor apparatuses require lengthy testing times due to the need for double testing to detect and verify defective memory cells, leading to low testing efficiency and increased costs, especially in large-scale integration scenarios like 1 Gbit DRAMs.

Innovation Solution

A redundancy circuit that uses electric fuses to program the address of defective memory cells and produces an irreparable-state signal when all fuses are used, allowing confirmation of address information only once, thereby shortening testing time and ensuring efficient operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If testing is carried out twice (once to extract defective memory cell and once to verify completion of repairing), then the defective memory cell can be reliably detected and repaired, but the testing time becomes excessively long and testing efficiency becomes low

Engineering Contradiction:
Improvedefective memory cell detection reliabilityVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the address information of the defective memory cell during the first testing phase and stores it in a register. This extracted address is then used directly in the second testing phase without requiring complete re-testing, thereby reducing the overall testing time while maintaining reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs preliminary extraction and storage of the defective cell address during the first testing phase. This preliminary action prepares the necessary information for the second testing phase, eliminating the need to re-detect the defective cell and thus reducing testing time.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If individual test programs are prepared for each product to test only around the repaired memory cell, then the testing time per product is reduced, but the man-hour required for preparation of multiple test programs increases

Engineering Contradiction:
Improvetesting time per productVSAvoidtest program preparation complexity
Core Design Contradiction:
Loss of timeVSEase of manufacture

Solution Approach 1:

The patent employs a single universal test program that can handle both the extraction of defective cells and the verification of repairs. The test program uses a register to store and retrieve address information, making it multi-functional and eliminating the need to prepare separate individual test programs for each product.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If laser trimmer is used to cut the fuse to program the address, then the address can be programmed into the fuse, but the defect cannot be repaired after assembling the semiconductor apparatus

Engineering Contradiction:
Improveaddress programming capabilityVSAvoidpost-assembly repairability
Core Design Contradiction:
Ease of manufactureVSEase of repair

Solution Approach 1:

The patent replaces the mechanical laser trimming process with an electrical programming method. The address is programmed into the fuse by applying a programming voltage that causes a controlled breakdown, creating a permanent conductive path. This electrical method allows for post-assembly repair capability while maintaining address programming functionality.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS7411845B2Redundancy circuit and semiconductor apparatus having the redundancy circuit
Publication Date: 2008.08.12 LONGITUDE LICENSING LTD
  • US7411845B2 patent drawing
  • US7411845B2 patent drawing
  • US7411845B2 patent drawing

AI summary

When a redundancy circuit is fully used and a further defect is present, an irreparable-state signal is produced. When the irreparable-state signal is produced, a defect is judged. When the irreparable-state signal is not produced, upon testing for quality judgment, extraction of a defective memory cell, programming an address of the defective memory cell into a fuse, and confirmation about whether or not the address is properly programmed are carried out. Quality judgment is possible only by confirming address information of the written address as confirmation after programming into the electric fuse.