Charge-Redistribution CIM Circuit for Low-Power Matrix Multiplication
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Solution Overview
Problem
The existing Compute-In-Memory (CIM) circuits face issues with high power consumption due to direct current processes, limited parallelism, and non-linear calculation results due to small parasitic capacitors, especially in vector matrix multiplications, which are crucial for artificial neural networks.
Innovation Solution
A compute-in-memory (CIM) circuit that includes a memory array, multiple MUXs, and a word line driver, which utilizes a memory array, multiple functional output units (MFUs), a plurality of MUXs, and a word line (WL) driver, where memory cells are paired and connected to grounded register capacitors, and operational amplifiers with feedback loops to perform charge redistribution, enabling vector matrix multiplication without direct currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct current processes are used in existing CIM circuits, then computation can be performed in memory, but power consumption increases
Solution Approach 1:
The patent employs periodic action by using alternating current (AC) signals instead of direct current (DC) for computation in memory. The circuit switches between different voltage states (e.g., VDD and VSS) in a periodic manner to perform matrix multiplication operations. This periodic switching enables computation while reducing static power consumption associated with continuous DC biasing, as the circuit only consumes power during active switching and computation phases.
2Quantity of substance
If small parasitic capacitors are used in memory cells, then memory density increases, but calculation results become non-linear
Solution Approach 1:
The patent introduces feedback mechanisms through operational amplifiers that read the differential voltage from memory cell pairs and apply corrective feedback to ensure linear calculation results. The op-amps amplify the small voltage differences generated by the parasitic capacitors during AC computation and provide feedback control to maintain linearity. This feedback approach allows the use of small parasitic capacitors for high memory density while compensating for non-linearity effects to achieve accurate computational results.
3Productivity
If memory cells are paired and connected to grounded register capacitors, then parallelism is enhanced, but circuit complexity increases
Solution Approach 1:
The patent merges multiple functions into unified circuit blocks to manage complexity while enhancing parallelism. Specifically, it combines the storage function (memory cells with parasitic capacitors), computation function (AC-based matrix multiplication), and readout function (differential amplification) into integrated memory-computation units. Each memory cell pair with its associated grounded register capacitor forms a functional unit that can operate in parallel with other pairs, achieving high parallelism through systematic integration rather than separate discrete components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CIM circuit reduces power consumption by eliminating direct currents and stabilizes bit-line voltages, enhancing energy efficiency and parallelism, while allowing for stable and efficient vector matrix multiplications.
Implementation Method 1
A grounded register capacitor is connected to a source line (SL) of each memory cell row
Implementation Method 2
utilizes a memory array, multiple functional output units (MFUs), a plurality of MUXs, and a word line (WL) driver, where memory cells are paired and connected to grounded register capacitors, and operational amplifiers with feedback loops to perform charge redistribution
Data Source
AI summary
A compute-in-memory circuit based on charge redistribution includes a memory array, multiple-functional output units (MFUs), multiplexers (MUXs), and a word line (WL) driver. The memory array includes memory cell rows and memory cell columns. Every two adjacent memory cells form a memory cell pair in sequence, and every two adjacent memory cell columns form a memory cell column pair in sequence. A grounded register capacitor is connected to a source line (SL) of each memory cell row. Input ends of each MFU are connected to a first bit line (BL) and a second BL of each memory cell column pair, respectively. Each MUX includes voltage-input ends and an output end, and the output end of each MUX is connected to the SL of each memory cell row in a one-to-one correspondence. An output end of the WL driver is connected to a WL of each memory cell row.