SRAM Bitline Boost via Short Pulse Write Clocks
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Solution Overview
Problem
Static random access memories (SRAMs) face challenges in reducing power consumption while maintaining high performance, particularly in mobile devices where power supply is limited, due to unwanted current flows during write operations.
Innovation Solution
The SRAM design incorporates a control logic that generates shorter pulse width write clock signals to reduce the duration of the turn-on voltage for selected word lines, along with a write driver that selectively discharges and boosts bit lines to a negative voltage, minimizing unwanted current flows and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the turn-on voltage is applied to the selected word line for a longer duration, then the write operation reliability is improved, but the power consumption increases due to unwanted current flows
Solution Approach 1:
The bit line is discharged to a negative voltage before the word line turn-on voltage is applied. This preliminary action ensures that when the word line is activated, the bit line is already in the correct voltage state, allowing for a shorter word line activation duration while maintaining write reliability and reducing unwanted current flows
Solution Approach 2:
The write operation uses clocked control signals with specific pulse widths to periodically activate the word line and control the discharge/boost operations. By optimizing the clock signal parameters, the system achieves reliable write operations with minimized activation duration, thereby reducing power consumption
2Productivity
If the write operation is performed faster, then the productivity is improved, but the write errors increase due to insufficient discharge time
Solution Approach 1:
The bit line discharge operation is initiated before the word line activation, ensuring that the discharge process begins early in the write cycle. This allows the bit line to reach the required voltage level even with shortened overall write time, maintaining write accuracy while improving speed
Solution Approach 2:
The system changes the voltage parameter of the bit line to a negative voltage level during the write operation. This parameter change enables faster discharge timing while ensuring sufficient voltage differential for reliable write operations, thus improving both speed and accuracy
Data Source
AI summary
A static random access memory includes a memory cell array, a control logic configured to generate a first write clock signal and a second write clock signal each of which having a pulse width shorter than a pulse width of a clock signal in response to the clock signal, a row decoder configured to select a word line in response to the second write clock signal during a write operation, a column selector configured to select a bit line and an inverted bit line, a sense amplifier configured to sense states of the selected bit line and the selected inverted bit line during a read operation and a write driver configured to bias the selected bit line and the selected inverted bit line in response to the first write clock signal during the write operation.